Crossware to Support C8051F12X and C8051F13X Chips from Silicon Laboratories.CAMBRIDGE, England -- Crossware (www.crossware.com), a leading embedded tools developer, has added full support to its 8051 Development Suite for the Silicon Laboratories (www.silabs.com) C8051F12X and C8051F13X mixed signal microcontroller units (MCUs). The Silicon Laboratories' chips feature advanced pipelining and caching and a phase locked loop which together allow the core to run at up to 100MIPS (Million Instructions Per Second) The execution speed of a computer. For example, .5 MIPS is 500,000 instructions per second; 100 MIPS is a hundred million instructions per second. . A multiply and accumulate (MAC) engine can also perform a 16-bit signed multiplication in two cycles. The Crossware enhancements allow developers to rapidly exploit the advanced features of these chips by providing a thorough combination of wizards, simulation, debugging, compiler extensions and pre-configuration. Code Creation Wizards are provided for all on-chip peripherals. They allow the phase locked loop to be rapidly configured to exploit the 100MIPS maximum performance and with the compiler and libraries using multiplication code that exploits the MAC engine, developers can instantly take full advantage of the speed offered by these chips. The Crossware environment is fully pre-configured to take advantage of the MCU's 128k bytes of in-system programmable Refers to programmable logic chips (PLDs) that are programmed after they are attached to the circuit board. Also called "in-circuit programmable," devices that use static RAM (SRAM) are in-system programmable by nature because they are loaded at startup. See PLD. banked flash and when simulating and debugging the banking process is virtually transparent to the developer. In addition, the flash memory Code Creation Wizard will generate all the code necessary to erase and rewrite flash memory during program execution. Crossware's source level debugger drives the Silicon Laboratories' JTAG (Joint Test Action Group) An IEEE standard for boundary scan technology. See scan technology. JTAG - Joint Test Action Group emulation cartridge directly. This allows it to make use of the full range of on-chip debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. facilities including the hardware data breakpoints and hardware stack overflow An error condition that occurs when there is no room in the stack for a new item. This error condition can also occur when other things go awry; for example, a bad expansion board or one that isn't seated properly in the slot can cause erratic signals eventually leading to a stack and underflow (1) An error condition that occurs when the result of a computation is smaller than the smallest quantity the computer can store. (2) An error condition that occurs when an item is called from an empty stack. trap. Crossware's 8051 development suite includes a full featured ANSI C (language, standard) ANSI C - (American National Standards Institute C) A revision of C, adding function prototypes, structure passing, structure assignment and standardised library functions. ANSI X3.159-1989. cgram is a grammar for ANSI C, written in Scheme. compiler, a relocatable cross-assembler, an advanced overlay linker, a state of the art source level simulator that can be extended to simulate a complete target system and a debug monitor which supports source level debugging on the target system itself. All of these integrate into Crossware's Embedded Development Studio development environment. For more information please contact Alan Harry, Crossware, Old Post House, Silver Street, Litlington, Royston, Herts, SG8 0QE, UK, tel: + 44 (0) 1763 853500 or fax + 44 (0) 1763 853330, alan@crossware.com. |
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