Crosspoint Solutions unveils advanced super-fine grained customer-programmable ASIC architecture, outlines future 100K gate product line.

MILPITAS, Calif.--(BUSINESS WIRE)--Dec. 4, 1995--Crosspoint Solutions Inc. disclosed today an advanced new architecture for very high gate count customer-programmable application-specific integrated circuits (ASICs).

In addition, the company provided a preview of a six-chip product family of programmable gate arrays having densities up to 100,000 gates that will be released during 1996.

The "CrossFire(TM)" proprietary architecture is the first to combine the power of state-of-the-art ASIC design methodology with high-density, high-performance customer-programmable products. According to the company, CrossFire products will be the world's first true customer programmable gate arrays that are compatible with existing ASIC design methodologies, gate densities and performance levels.

According to Robert N. Blair, President and CEO, "CrossFire sea-of-gates architecture is the foundation of Crosspoint Solutions' next product family which will enable customers to punch through the 50K gate design wall. Users will get a real 60 to 80% gate utilization with their designs, and with up to 100K gates, we'll see the birth of an entirely new system-level customer-programmable ASIC market," Blair said.

The new CrossFire architecture employs a proprietary super-fine grained half-gate basic building block called a CoreCell(TM). Two CoreCells can be arranged to form a 2-input NAND gate or a latch storage cell. This approach has been optimized for mainstream ASIC synthesis-based design methodology and efficiently implements both memory and logic.

The CrossFire product family will be implemented in a 0.5-micron, 3/4-layer metal CMOS technology, and initially will consist of six devices having gate counts from 20,000 to 100,000. The CrossFire technology road map calls for eventual process migration to a 0.25-micron technology resulting in chips at 250K and beyond gate levels.

The CoreCell technology uses a sea-of-gate's architecture and the MicroFuse(TM) amorphous silicon antifuse technology. Individual CoreCells are arranged in cell clusters called a "Tray." The Trays are distributed over the die as a sea-of-gates, forming a "Sea-of-Trays(TM)" array. These Trays are compactly placed on the chip in a seamless "fabric" that substantially reduces interconnect delays and, at the same time, dramatically increases routing resources.

The Trays are connected together using a unique hierarchy of routing resources to implement functions. These are IntraTray Routing, InterTray Routing and Multiple Global Signal Grids.

IntraTray routing, the lowest level of routing resource, is used to connect CoreCells within a Tray. InterTray routing spans adjacent Trays, and is used for intermediate length routing across Tray boundaries. Multiple Global Signal Grid resources span the die to provide fast, high fanout global signals. Maximum skew across a clock grid is less than 1 ns.

CrossFire ASIC++(TM) Design Environment

CrossFire technology and the coming product family was developed with the objective of providing optimum results in density and performance using the same EDA design tools and methodologies used in today's system-level ASIC designs.

Front-end design is accomplished through the use of Synopsys, Mentor Graphics, Cadence, Viewlogic or other industry-standard third-party tools. These are supported by Crosspoint Solutions' design kits containing primitive cell library elements optimized for HDL-based, top-down design techniques. The use of this methodology is a critical prerequisite to the achievement of rapid design success with high-density arrays. When an initial design is completed, a netlist is generated and read by the CrossFire back-end design suite called the ASIC++ Design System.

The ASIC++ Design System consists of several tools including: Cross Examiner, Design Floorplanner, Timing-Driven Place and Route, and Time Checker.

The ASIC++ Design System will be offered for both UNIX- and Windows-based design platforms, and will be formally introduced with the CrossFire product releases.

System-Level Cores and Libraries

The CrossFire ASIC family will be supported by a rich set of system-level cores and industry-standard ASIC hard and soft macrocell functions. Included will be:

-- Memory structures created via memory compilers that will automatically generate RAM, ROM, FIFO and register file structures. Multiple ports and control structures will be user-definable.

-- Parameterized MSI functions such as adders, LFSRs, ALUs that allow user-defined function widths and control signals when needed.

-- Application-specific core functions at the system-level such as DSP engines, graphic accelerators, and ATM framers will be available to support high-density customer-programmable ASIC designs.

-- An extensive set of hard and soft industry-standard ASIC macrocell functions will be supported by the CrossFire library including NANDs, NORs, flip-flops, buffers, latches, inverters, clock drivers, complex gates and I/Os.

CrossFire Product Description

The CrossFire CP100K product family will number six devices having density ranges from 20,000 to 100,000 gates. The operating voltage for the family will be 3.3 volts, and will have an operating speed of up to 100 MHz. The table provides a snapshot of the CP100K family.

The CrossFire CP100K Product Family -0-

             Available
P/N       Gate Array Gates   Usable Gates    Usable Bits      I/O
---       ----------------   ------------    ------------     ---
CP20K         20,000         12,000-15,000      10,000      100-220
CP36K         36,000         24,000-28,000      18,000      100-300
CP48K         48,000         32,000-36,000      24,000      160-350
CP62K         62,000         40,000-46,000      31,000      160-350
CP84K         84,000         50,000-58,000      42,000      208-400
CP100K       100,000         60,000-70,000      50,000      208-450

CrossFire Family Product Features:

         --  ASIC density and performance
         --  100 MHz system operation, 3.3 V operation
         --  ASIC design methodology, libraries and cores
         --  Rich I/O options:
                 o User-configurable as inputs, outputs or
                    bidirectional
                 o 8- or 16-mA drive
                 o Slew rate control
                 o 3-state control
                 o PCI compatible
         --  Secure programming with Crosspoint Solutions'
             MicroFuse(TM) antifuse technology
         --  0.5-micron, 3/4-layer metal CMOS technology-0-

Crosspoint Solutions Inc. was founded in 1989 to develop and market the first real fully user-programmable Gate Array. The company's FPGAs feature compatible gate array architecture, and employ the same industry-standard EDA (design) tools and libraries as the leading ASIC vendors. The company's address is 694 Tasman Drive, Milpitas, Calif. 95035. The telephone number is 408/324-0200, the facsimile number is 408/324-0123 and email is: [e-mail]. -0-

Note to Editors: 1. The Crosspoint Solutions logo and logotype is a registered trademark belonging to Crosspoint Solutions Inc. "CrossFire, MicroFuse, Sea-of-Trays" and "ASIC++" are trademarks belonging to Crosspoint Solutions Inc. "Windows" is a trademark belonging to Microsoft Corporation.

2. Acronym, Abbreviation key: NAND = A "Nor-And" Gate, EDA = Electronic Design Automation, HDL = High-level Design Language, PCI = Personal Computer Interconnect, DSP = Digital Signal Processor, FPGA = Field Programmable Gate Array, ROM = Read Only Memory, RAM = Random Access Memory, FIFO = First-in First-out Memory, ALU = Arithmetic Logic Unit, MSI = Medium Scale Integration, ATM = Asynchronous Transfer Mode, LFSR = Linear Frequency Shift Register.

CONTACT: Crosspoint Solutions Inc.

Michael Levis, 408/324-0200

or

Alfaro Company

Kim Alfaro, 415/563-4769