Credence Announces Production Release of the EPRO AQ Series for Integrated Test and Back-end Processing.WASHINGTON--(BUSINESS WIRE)--Oct. 23, 1995--Credence Systems Corporation (Nasdaq: CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. ) today announced production release of the EPRO AQ Series. The AQ is the industry's first system to provide true, turnkey integration of multiple back-end processing operations including test, handling, cycling, inspection, and mark for FLASH, EEPROM (Electrically Erasable Programmable ROM) A rewritable memory chip that holds its content without power. Although EEPROMs spawned flash memory, EEPROMs are byte addressable at the write level, whereas flash chips must erase a block of bytes before rewriting. , SRAM See static RAM. SRAM - static random-access memory , and DRAM, as well as non-memory devices. Credence is demonstrating the EPRO AQ this week at the International Test Conference in Washington, D.C. The new EPRO AQ Series combines multiple process steps -- including pre-test, cycling, post-test, inspection, mark, and category sort -- on a high-speed, pick-and-place handling platform. This integrated approach dramatically improves manufacturing throughput and cost efficiencies. The system can test up to 4 devices in parallel at both pre-test and post-test stations while simultaneously cycling up to 256 devices. The EPRO AQ handles a full range of package types, including thin small outline (TSOP (Thin Small Outline Package) A very thin, plastic, rectangular surface mount chip package with gull-wing pins on its two short sides. TSOPs are about a third as thick as SOJ chips. See gull-wing lead, SOP, SOJ and chip package. ), quad flat pack (QFP), small outline (SOP), plastic leaded chip carrier A Plastic Leaded Chip Carrier (PLCC) is a four-sided “J”-leaded plastic integrated circuit package with pin spacings of 0.05" (1.27 mm). Lead counts range from 20 to 84. PLCC packages can be square or rectangular. Body widths range from .35" to 1.15". (PLCC (Plastic Leaded Chip Carrier) A plastic, square, surface mount chip package that contains leads on all four sides. The leads (pins) extend down and back under and into tiny indentations in the housing. See chip package. ), and dual in-line pin (DIP) packages. A standardized, modular approach to the design permits custom configuration by the user of the component functions. Included in the presently available modules are the AQ EDGE Testing System, an asynchronous Refers to events that are not synchronized, or coordinated, in time. The following are considered asynchronous operations. The interval between transmitting A and B is not the same as between B and C. The ability to initiate a transmission at either end. , multi-site adaptation of the industry standard EDGE tester; and the AQ WAVE Cycling System, a non-volatile memory cycler adaptation of the popular WAVE cycling system. With a placement accuracy of 0.1 thousandths of an inch, the EPRO AQ handling base eliminates the need for separate cycling board loaders and test handling equipment. The standardized architecture permits integration of new capabilities with minimal reconfiguration. "By housing numerous processes within just 10% of the floorspace, the AQ eliminates several operator interventions," explained Mark Allison, Director of Memory Products Marketing. "And with fewer loading and unloading operations, process time is reduced by up to a factor of three. This streamlined operation also significantly reduces yield loss from lead damage and electrostatic discharge." Several systems are now in production at customer locations in the United States and in Europe. The EPRO AQ supports I/O from either JEDEC The division of the Electronic Industries Alliance (EIA) that deals with semiconductor standards (officially, the JEDEC Solid State Technology Association of EIA). JEDEC was formed in 1958 when the Joint Electron Tube Engineering Council (JETEC) split into two Joint Electron Device trays or tubes. Real-time monitoring of the vacuum pickups, test sites, and other sensors is displayed on the system monitor. Pricing for the EPRO AQ Series starts at $250,000. ABOUT THE AQ EDGE Testing System The AQ EDGE Testing System is an asynchronous, multi-site test module for FLASH, EE, and other non-volatile memory devices. This module features two truly independent testing resources to provide maximum flexibility and throughput. Even the pattern generator and redundancy checking and repair resources are separate for each device under test. For those test applications requiring even higher parallelism, the AQ EDGE can also be configured for shared-resource testing to allow simultaneous test of up to 16 serial EE devices or 4 parallel devices. ABOUT THE AQ WAVE Cycling System The AQ WAVE Cycling System module automatically cycles, tests, and characterizes the endurance of all FLASH and EE device types. The module characterizes all FLASH topographies including NAND (Not AND) A Boolean logic operation that is true if any single input is false. Two-input NAND gates are often used as the sole logic element on gate array chips, because all Boolean operations can be created from NAND gates. See flash memory. cells, NOR, DINOR and other electrically erasable architectures. The AQ WAVE may be configured into multiple zones, allowing users to cycle smaller lots of several different device types or perform a variety of tests simultaneously on the same system. Applications include characterization, margin analysis, and gross functional testing. Credence Systems Corporation is a leading manufacturer of automatic test equipment (ATE) that serves a broad spectrum of the worldwide semiconductor industry's testing needs. Credence, together with its wholly owned subsidiary Wholly Owned Subsidiary A subsidiary whose parent company owns 100% of its common stock. Notes: In other words, the parent company owns the company outright and there are no minority owners. , EPRO, offers a wide range of products with test capabilities for digital, mixed-signal, and non-volatile memory semiconductor devices. Credence utilizes its proprietary CMOS technologies to redefine test by designing products that solve its customers' business problems through technology while meeting the increasingly demanding performance requirements of today's ATE market. The Company is headquartered in Fremont, California, with manufacturing in Beaverton, Oregon and Santa Clara, California Santa Clara, California (IPA: /ˌsæntəˈklærə/) , founded in 1777 and incorporated in 1852, is a city in Santa Clara County, in the U.S. state of California. . Credence is listed on the Nasdaq National Market under the symbol CMOS. CONTACT: Credence Systems Corp. Henry S. Kim, 510/623-4739 or IPRA IPRA International Public Relations Association IPRA International Peace Research Association IPRA Illinois Park and Recreation Association IPRA International Professional Rodeo Association IPRA Internet Policy Registration Authority Dick Davies, 415/777-4161 |
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