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Cray implements Denali's Databahn memory controller cores, uses MMAV software for memory modeling and simulation.

Denali Software Inc., has announced that Cray Inc. (Nasdaq NM: CRAY) has selected its Databahn memory controller intellectual property (IP) cores and MMAV verification IP software for next-generation supercomputer product development.

Cray plans to use Denali's Databahn IP in the design of the DDR-SDRAM DDR-SDRAM - Double Data Rate Random Access Memory  memory system for its next-generation chips. Cray will also use Denali's MMAV product for modeling and simulating the interactions between its chips and external memory devices for design verification and performance analysis.

Says Dave Kiefer, vice president of engineering at Cray: "Designing supercomputers demands leading-edge EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board.  tools and IP. We selected Denali's MMAV and Databahn controller cores based on the product capabilities as well as Denali's reputation for quality and reliability."

"Cray stands apart as a leader in the supercomputer race," adds David Lin, Denali's vice president of applications engineering. "By providing Cray with memory controller cores and verification software, we are helping them continue to meet their rigorous standards for quality and performance."

Licensed for use in more than 100 designs by leading semiconductor and system companies, and with more than 35 chips in production, Databahn is the industry-leading memory controller IP solution. Databahn cores are configurable for a wide range of performance and power requirements, as well as ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor.  interfaces.

To ensure compatibility with all the latest high-speed memory technologies, the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM (Synchronous DRAM) A type of dynamic RAM (DRAM) memory chip that has been widely used since the late 1990s. SDRAM chips eliminated wait states by dividing the chip into two cell blocks and interleaving data between them. , DDR (Double Data Rate) Refers to an SDRAM memory chip that increases performance by doubling the effective data rate of the frontside bus. For more details, see SDRAM.

DDR - Double Data Rate Random Access Memory
1-SDRAM, DDR2-SDRAM, and Mobile DDR-SDRAM devices from all major memory vendors.

Deliverables include: register transfer level (RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; ) and synthesis scripts, silicon-independent DDR PHY See physical layer and physical. , verification testbench, static timing analysis (STA) scripts, programmable register settings and documentation.

The silicon-proven Databahn IP is library independent and covers solutions from .18-micron to .08-micron technologies, and DRAM device frequencies from 100-400MHz (200-800MHz data rate).
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Title Annotation:Denali Software Inc.
Comment:Cray implements Denali's Databahn memory controller cores, uses MMAV software for memory modeling and simulation.(Denali Software Inc.)
Publication:EDP Weekly's IT Monitor
Geographic Code:1USA
Date:Aug 9, 2004
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