Cray, Inc. Uses Synopsys' Physical Synthesis to Tape Out Eight Million-Gate, 450 Mhz, 1.8 Gigaflop Vector CPU ASIC for New SV1e Supercomputer.Business Editors/High-Tech Writers Physical Compiler Helps Achieve Target Performance with Significant Savings in Design Time MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Nov. 7, 2000 Synopsys, Inc. (Nasdaq:SNPS SNPS Space Nuclear Power System ) today announced that Cray Inc. (Nasdaq:CRAY) has successfully taped out Refers to the completion of the design of a chip. The next stage is to put it into production. The term comes from the early days when designs were transferred to the fabricator via magnetic tape. an eight million-gate, 450 MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. , vector processor ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. using Synopsys' Physical Compiler. The design was implemented using a copper-based 0.12-micron process technology. The chip, code named Processor Vector Cache (PVC PVC: see polyvinyl chloride. PVC in full polyvinyl chloride Synthetic resin, an organic polymer made by treating vinyl chloride monomers with a peroxide. ), is being used in the new Cray SV1e(TM) scalable-vector supercomputer, which was announced today at the IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. Supercomputing 2000 conference in Dallas, Texas. Cray incorporated Physical Compiler into its ASIC flow as a CAD tool enhancement to achieve aggressive SV1e project objectives. Cray was able to use Physical Compiler with less than a week of startup effort, by leveraging its current Design Compiler infrastructure. With Physical Compiler central to their timing-closure flow, Cray achieved their very aggressive circuit performance goals while saving significant design time. "As a builder of the world's most capable supercomputers, Cray is constantly pushing the limits of circuit design," said Gary Shorrel, Cray SV1e engineering project manager. "The PVC chip was difficult even by Cray's standards, and achieving timing closure was a significant challenge. Using Physical Compiler's capabilities enabled us to achieve our aggressive target frequencies. Physical Compiler fit right into our ASIC flow and we were able to get up to speed in under a week. Physical Compiler reduced the overall design cycle and eliminated the painful iterations by enabling placement handoff to the ASIC vendor." "Cray's ASIC designs challenge even the most sophisticated vendor flows in achieving timing closure," said Sanjiv Kaul, senior vice president and general manager of the Physical Synthesis business unit at Synopsys. "In addition to helping our customers achieve their target performance goals in the shortest time, Physical Compiler's placement handoff is adding predictability into the flow, allowing them to meet their time to market requirements." Synopsys' Physical Synthesis Solution Pioneered by Synopsys, Physical Synthesis helps designers address the implementation challenges of next-generation system-on-chip designs. Physical Synthesis brings key physical design considerations forward in the design flow, allowing RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; designers to rapidly achieve high quality of results. The overall design flow includes Chip Architect design planner, Physical Compiler unified synthesis and placement, and FlexRoute top-level router. Synopsys' Physical Synthesis leverages industry-standard tools such as Design Compiler(TM), Module Compiler(TM) and PrimeTime(R) and its proven interfaces to third-party solutions allow it to easily plug into an existing design flow. About Cray Inc. Cray Inc. is the global market leader in high-end supercomputers. Cray Inc. is dedicated to helping customers solve the most demanding, most crucial computing problems on the planet -- designing the cars and trucks we drive, creating new materials and life-saving drugs, predicting severe weather and climate change, analyzing complex data structures, safeguarding national security, and a host of other applications that benefit humanity, by advancing the frontiers of science Frontiers of Science was a popular illustrated comic strip created by Professor Stuart Butler of the School of Physics at the University of Sydney in collaboration with Robert Raymond, a documentary maker from the Australian Broadcasting Corporation (ABC) in 1962. and engineering. Visit Cray Inc. at http://www.cray.com/company/about.html About Synopsys Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California For the census-designated place, see Mountain View, Contra Costa County, California. For other places called "Mountain View", see . Mountain View is a city in Santa Clara County, in the U.S. state of California. The city gets its name from the views of the Santa Cruz Mountains. , creates leading electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services support services Psychology Non-health care-related ancillary services–eg, transportation, financial aid, support groups, homemaker services, respite services, and other services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com. Note to Editors: Synopsys and PrimeTime are registered trademarks, and Design Compiler and Module Compiler are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners. |
|
||||||||||||||||
Printer friendly
Cite/link
Email
Feedback
Reader Opinion