ControlNet Releases TCP/IP Stack Verification Intellectual Property for OpenVera Hardware Verification Language.

Business Editors/High-Tech Writers

CAMPBELL, Calif.--(BUSINESS WIRE)--Dec. 9, 2002

OpenVera Verification Module for TCP/IP Stack Standard Cuts Down Time

to First Test

ControlNet India Pvt. Ltd., a leading provider of electronic Integrated Circuit (IC) and software development services, today announced the immediate availability of TCP/IP Stack OpenVera(TM) verification intellectual property (IP). This verification IP provides pre-verified, standards-compliant, plug and play OpenVera modules that cut down overall verification time for engineers validating TCP/IP Stack-based designs.

"ControlNet is a leading provider of design services and verification IP for networking and connectivity markets," said P. Sridhar, CEO of ControlNet India. "Our team has in-depth exposure on all layers of networking, from the physical layer to the application layer, and has built an extensive verification environment for our clients. The TCP/IP Stack verification IP for OpenVera enables users to quickly generate the TCP/IP protocols to test and validate their designs for IP, TCP, ICMP, and UDP features. In addition, this verification IP enables our customers to generate packets at the application layer to improve the efficiency of test generation."

TCP/IP stack OpenVera models support IPv4, TCP, UDP, and ICMP protocols. The verification IP provides random traffic generators and monitors for design under test (DUT) -- which supports the aforementioned protocols -- and provides the exhaustive compliance suite to test the DUT's compliance to given protocols. The verification IP will also facilitate DUT testing, which implements TCP/IP Stack in silicon, such as routers, switches and network connectivity design cards.

"Verification IP is an integral component of the verification environment. It provides enhanced productivity to system and ASIC designers by reducing the time to create the verification infrastructure and testbench environment, including the required models," said James Watts, OpenVera program manager at Synopsys, Inc. (Nasdaq:SNPS) "OpenVera verification IP gives users the ability to test against the standard without the need to learn all of the standard's details, greatly reducing overall verification time."

Key Features of ControlNet's OpenVera Verification IP:

ControlNet's OpenVera verification IP supports protocols TCP, Ipv4, UDP, ICMP (echo and echo reply packets only). The verification IP comes with a compliance test suit to validate IP, TCP, ICMP and UDP protocol implementation. The following is a partial list of TCP/IP verification features. For a complete list of features, including UDP and ICMP features, visit our website: www.controlnetindia.com/ip.php.

IP Features:

-- Programmable IP header for all packets

-- IP checksum calculation and checking

TCP Features:

-- Connection establishment process for TCP connection

-- Programmable maximum number of TCP connection, maximum number

of listen ports

-- Transmission and reception of TCP packets

-- TCP packets are fully programmable

-- Supports following optional data fields in TCP packets:

maximum segment size, window scale factor and time stamp

-- Error forcing in TCP packets

-- Sends acknowledgement packets in response to correct TCP

packet received

-- While transmission and reception packets are dumped to log

file

-- Hex dump for transmitted and received packet is also supported

-- Display of error in the packet (if any) and also error

information register for user or application purpose

-- Connection termination and abort process

-- Connection timeout and packet retransmission

-- Programmable keep alive timer, sending keep alive probe and

programmable persistent timer

-- TCP checksum calculation and checking

Pricing and Availability

The TCP/IP Stack OpenVera verification IP is available now and supports Verilog and VHDL designs. It comes with full documentation and sample test cases. Please contact: [e-mail] for pricing information.

About OpenVera and OpenVera Assertions

OpenVera is an open source hardware verification language developed to meet the unique requirements of functional verification. OpenVera Assertions (OVA) is a high-level language that contains powerful declarative constructs for accurately capturing design specification and is useful in both dynamic and formal verification environments. With these languages, design and verification engineers describe the target application environment, including complex protocols and data objects, at a high level of abstraction, which significantly improves productivity, readability and reusability. For more information on OpenVera and OVA, visit www.open-vera.com.

About ControlNet India

ControlNet India is a wholly owned subsidiary of ControlNet Inc, headquartered in Campbell, California, USA. ControlNet India delivers state-of-the-art ASICs, IP cores, rapid proto-typing (FPGA), design consulting services and software to the global electronics industry. ControlNet India offers total one-stop solutions for SoC realization, featuring RF, analog and mixed-signal ASIC capabilities. The mission is to create a world-class organization, by creating a center of excellence with continuous technology innovation and focused to achieve customer satisfaction through PACT- Performance, Accuracy, Cost effectiveness and Timeliness.

ControlNet India develops and delivers design solutions right from concept to systems in niche areas using the latest technology and tools from leading EDA vendors. To learn more, please visit http://www.controlnetindia.com/

Synopsys is a registered trademark of Synopsys, Inc. OpenVera is a trademark of Synopsys. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.