Computer architecture and high performance computing; proceedings.9780769534237 Computer architecture and high performance computing computing - computer ; proceedings. International Symposium on [title] (20th: 2008: Gramado, MS, Brazil) Ed. by Edson Norberto Caceres et al. Computer Society Press 2008 192 pages $196.00 Paperback QA76.9 These proceedings from the October/November 2008 symposium focus on computer architecture and high performance computing. Once centered on the work of Brazilian researchers, the 85 contributors here include 41 non-Brazilians. They address architecture, accurate and low overhead dynamic detection and production of program phases using branch signatures, aggressive scheduling in multithreaded multithreaded - multithreading architectures, optimization mechanism intended for two level cache hierarchies, such applications as simulated annealing simulated annealing - A technique which can be applied to any minimisation or learning process based on successive update steps (either random or deterministic) where the update step length is proportional to an arbitrarily set parameter which can play the role of a temperature. for the scheduling of parallel applications and controlling process reassignment in applications, multicore methods, including a methodology for developing high fidelity high fidelity n. The electronic reproduction of sound, especially from broadcast or recorded sources, with minimal distortion. high communication models for large scale applications, applications to parallel verified linear system solvers for uncertain input data, operating systems Operating systems can be categorized by technology, ownership, licensing, working state, usage, and by many other characteristics. In practice, many of these groupings may overlap. (including graded and cluster systems) performance sensitivity and memory operations. ([c]20082005 Book News, Inc., Portland, OR) |
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