Component-based EDA Software Companies, Verific and SoftJin, Team Up; SoftJin's Programmable Synthesis Engine Integrates with Verific's Front End.ALAMEDA, Calif. and BANGALORE, India -- SoftJin, a customized EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. (Electronic Design Automation) software development services company, and Verific Design Automation today announced that SoftJin's Programmable Synthesis Engine (PSE PSE 1. pale soft exudative pork. 2. portosystemic encephalopathy. ), a logic optimization and mapping software product that is customizable for a variety of programmable platform architectures, has been integrated with Verific's Hardware Description Language (language) Hardware Description Language - (HDL) A kind of language used for the conceptual design of integrated circuits. Examples are VHDL and Verilog. (HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. ) component software. By using individual best in class components from SoftJin and Verific, and pre-verifying those components together, customers get the most value and choose the most appropriate synthesis solution at the most optimal cost. According to Nachiket Urdhwareshe, SoftJin's CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. , "We worked with the defacto leader in the HDL front-end component software space, Verific, to integrate their proven HDL front end with our Programmable Synthesis Engine so that our programmable platform customers have access to seamlessly integrated Synthesis solution from RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; onwards." Customers can choose from VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. , Verilog and SystemVerilog input and feed the output of any of these components into SoftJin's Synthesis engine. On the back end, based on the customizable technology specific optimization and mapping solution built into PSE, the customer can maximize the Quality of Results of the synthesis process by tailoring the mapping and the optimization to its own individual fabric. "Our companies have the same goal--to provide EDA components for EDA software developers and in-house EDA groups building their own tools," added Michiel Ligthart, Verific's chief operating officer Chief Operating Officer (COO) The officer of a firm responsible for day-to-day management, usually the president or an executive vice-president. . "By working together to integrate Verific's HDL Front End with SoftJin's Programmable Synthesis Engine, we are able to offer them a more complete component-based solution that includes the front-end as well as a custom synthesis engine." About SoftJin's PSE SoftJin's PSE is a customizable Synthesis engine that allows its users to derive the most from the underlying architecture of a programmable platform. It delivers better Quality of Results (QoR) when compared to traditional FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. and ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. synthesis tools. SoftJin customizes each PSE to specific programmable platform architecture and for integration with placement and routing tools. PSE is licensed by programmable platform vendors for use by their customers who are FPGA, ASIC or SoC designers. PSE can also be licensed by system-level EDA companies who would like to extend their offerings into the RTL domain. About Verific Design Automation Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog, VHDL and PSL/Sugar front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: info@verific.com. Website: http://www.verific.com. About SoftJin SoftJin Technologies Pvt. Ltd. develops customized EDA tools for the specific requirements of semiconductor and EDA companies using a combination of EDA software development services and re-usable Building Blocks. SoftJin's customized EDA software development approach offers the advantages of enhanced EDA software capability, flexible capacity and cost savings to customers. SoftJin has also been recently (Aug 2006) chosen as one of the top 100 private companies in Asia that play a leading role in innovation and technology by Red Herring Red Herring A preliminary registration statement that must be filed with the SEC describing a new issue of stock (IPO) and the prospects of the issuing company. Notes: magazine. More information is available at www.softjin.com. The company's headquarters are located at Unit No: 102, Mobius Tower, SJR SJR Senate Joint Resolution SJR Superjoint Ritual (band) SJR St John Rigby (Catholic Sixth Form College) SJR Signal-To-Jammer Ratio SJR Saint Joseph Regional High School (USA) I - Park, EPIP, White Field, Bangalore - 560066, Tel: +91-80-41779999, E-mail: sales@softjin.com The USA office is located at 2900 Gordon Ave, Suite 100-11, Santa Clara, CA 95051, Tel: (408) 773-1714, Email: sales_us@softjin.com Note to Editors: An illustration detailing how SoftJin's PSE and Verific's HDL Component Software work together is available upon request. Requests should be made to: Georgia Marszalek, ValleyPR for SoftJin, +650-345 7477, Georgia@ValleyPR.com Nanette Collins, Public Relations for Verific, (617) 437-1822, nanette@nvc.com SoftJin and Verific acknowledge trademarks or registered trademarks of other organizations for their respective products and services. |
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