CompiLogic Introduces New Product for Accelerating Data-Flow and DSP IC Design; New ANSI C to RTL Verilog Compiler Enhances User Control of Hardware Operations.

SAN FRANCISCO--(BUSINESS WIRE)--June 9, 1998--CompiLogic today announced C2Verilog Pro, the latest product in its family of high-end Electronic Design Automation tools.

C2Verilog Pro will debut at the Design Automation Conference held in San Francisco, June 15 - 17, 1998. Specifically designed to accelerate the design of data flow and Digital Signal Processing (DSP) hardware applications, C2Verilog Pro automatically compiles ANSI C designs and algorithms into Register-Transfer-Level Verilog which can be synthesized into FPGA and ASIC hardware.

C2Verilog Pro, available on both UNIX and Windows platforms, enables users to exert greater control over the compilation process. With more control over how each operation is implemented, users can determine appropriate trade-offs between hardware resources and the number of clock cycles. The result is dramatically improved hardware resource efficiency and faster execution times.

Specifically, C2Verilog Pro enables greater user flexibility and control with the parallel execution of loop iterations, better definition of register arrays and the overall sharing of resources. For example, 'C' variables and arrays can be optionally mapped into sequentially addressed external chip memory or into registers which can also be accessed in parallel.

C2Verilog Pro also simplifies the implementation of DSP algorithms in hardware. Complicated algorithms previously compiled for software execution in standard DSP ICs can now be compiled into IC hardware for faster gate-level execution.

"C2Verilog Pro lets the user be the driver," said Don Soderman, chief executive officer of CompiLogic. "Using the product, system designers can guide their design through a highly interactive GUI and insertion of pragmas in their C code. They can proactively control the clock cycle efficiency and hardware resources in RTL before they move into hardware design.

"Beta users have been astounded at the results achieved -- generating in a few minutes nearly the same hardware efficiency as that manually generated with over a month of engineering effort."

Beta users have used this product to compile RSA encryption algorithms, JPEG compression algorithms, FIR filters and other DSP functions described in C. They have also synthesized designs for implementation in ASIC and FPGA hardware.

Companies with unique intellectual property algorithms can use C2Verilog Pro to safeguard their investment by distributing technology specific hardware descriptions versus C-based descriptions of products in development. In addition, C2Verilog Pro can be used to rapidly prototype secure product designs using programmable hardware.

C2Verilog Pro fills another gap in the design process and provides an even more sophisticated alternative to behavioral synthesis, according to Soderman. The compiler performs global analysis to create the optimum description for parallel execution.

It creates synthesizable RTL Verilog with a combination of concurrent assignments and multiple always blocks. State machines are automatically created to access variable storage in memory and other complex arithmetic functions (multipliers, filters, etc.).

Like CompiLogic's other compiler, C2Verilog, C2Verilog Pro accepts the entire ANSI C language with pointers, structures, arrays, user-driven shared hardware (memory and logic) resources and even recursion. Results can be further enhanced by following C-coding guidelines suggested by CompiLogic.

Also following the same model as other CompiLogic products, C2Verilog Pro complements existing logic synthesis and simulation modeling products. The generated RTL Verilog code is compatible with industry standard logic synthesis products from Synopsys, Exemplar and Synplicity as well as Verilog simulators from Cadence, Model Technologies and others. C2Verilog Pro includes automatic Verilog test-bench generation from C to accelerate design verification.

C2Verilog Pro is immediately available on Windows (95/NT) or UNIX (SunOS/Solaris) and is priced at $25,000 for node-locked licenses. The product includes an enhanced C to Verilog simulation test-bench capability for design verification.

Founded early last year in San Jose, Calif., CompiLogic Corp. develops and markets products that utilize high-level C language to design FPGA and ASIC hardware. Advanced copies of CompiLogic products have been used by several engineering companies and government laboratories, including the NASA Jet Propulsion Lab in Pasadena, Calif.

For more information, contact CompiLogic Corp. at 2105 Hamilton Ave. #310, San Jose, CA 95125, 408/369-0555 or visit their web site at www.compilogic.com.

Beta User Contact: Eric Brewer, PicoStar Corp. 650/493-4900

    CONTACT: Crowley Communications
              Pam Crowley, 408/377-8384
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              CompiLogic Corp.
              Don Soderman, 408/369-0555
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