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Compass Furthers its Commitment to Formal Verification Arena; Provides Industry's Most Complete RTL-to-Silicon Tool Suite; Delivers VFormal Verilog, Enabling Industry's First Mixed-Language Environment; and Laybool, Industry's Only Functional Extraction Tool.


GENEVA--(BUSINESS WIRE)--Sept. 18, 1996--In an unprecedented move for the formal verification
"Verifiability" redirects here. For the Wikipedia policy, see Wikipedia:Verifiability.


In the context of hardware and software systems, formal verification
 arena, COMPASS Design Automation, Inc., a leader in electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) software and libraries for deep submicron design, today revealed two new verification tools that, when coupled with the company's current product offering, provide designers with the industry's most complete RTL-to-silicon formal verification tool suite.

Building on its industry-proven VFormal(TM) tool for VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction.  design, COMPASS today announced Verilog capability, giving designers the choice of powerful standalone Verilog formal verification, or the industry's first single-engine, mixed-language verification environment. Equally important, COMPASS announced Laybool(TM), the industry's only commercially available functional extraction tool. By combining VFormal with Laybool, designers now have access to the industry's only direct layout vs. RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences;  (LvRTL) formal verification environment.

"The formal verification market is growing at an extremely rapid pace, with an 80.6 percent year-to-year growth rate from 1994 to 1995," stated Gary Smith Gary Smith may refer to:
  • Gary Smith (Realtor Albuquerque NM)
  • Gary Smith (CEO of Ciena corporation)
  • Gary Smith (Irish Bassist)
  • Gary Smith (singer with Emencity)
  • Gary Smith (sportswriter)
  • Gary Smith (record producer)
  • Gary Smith (guitarist)
, principal analyst for the San Jose-based market research firm Dataquest. "With today's announcement from COMPASS of what looks to be the next-generation in formal verification, the company is poised to serve this growing market as one of its leaders."

"By using VFormal and Laybool together, we were able to quickly isolate and fix critical problems, such as unconnected wires, wrong polarity (1) The direction of charged particles, which may determine the binary status of a bit.

(2) In micrographics, the change in the light to dark relationship of an image when copies are made.
 of outputs, twisted busses, and the use of a cell from the wrong library that would have been difficult to detect without formal verification," stated Frederic Rocheteau, design engineer, SGS-Thomson Microelectronics. "Because of these benefits, we are not just using these tools for a final verification of the blocks but have implemented them throughout the entire design process."

Provides Industry's First Mixed-Language Verification Environment

The core technology of COMPASS' formal verification offering is VFormal, consisting of the new Verilog capability, the existing VHDL capability, and the new mixed-language environment based on a single verification engine. The combination of the Verilog and VHDL capabilities of VFormal marks the first time designers have had access to a mixed-language verification environment and provides capabilities such as comparing functional Verilog models to VHDL models, thereby eliminating the need for test vectors; migrating Verilog designs to VHDL and vice versa VICE VERSA. On the contrary; on opposite sides.  for design reuse; and verifying mixed VDHL/Verilog blocks and designs that contain Verilog or VHDL leaf cells. COMPASS also announced a new Motif graphical user interface graphical user interface (GUI)

Computer display format that allows the user to select commands, call up files, start programs, and do other routine tasks by using a mouse to point to pictorial symbols (icons) or lists of menu choices on the screen as opposed to having to
 (GUI (Graphical User Interface) A graphics-based user interface that incorporates movable windows, icons and a mouse. The ability to resize application windows and change style and size of fonts are the significant advantages of a GUI vs. a character-based interface. ) for VFormal, allowing designers to quickly and easily identify problems across multiple levels of design abstraction.

Utilized early in the design cycle, VFormal enables designers to: -0-

-- Identify "hard to find" bugs at the RT level before they

propagate to later design stages where they are more costly or

time consuming to fix

-- Verify the quality of their RTL code

-- Maintain that quality via functional equivalence checking

throughout the design process. -0-

Due to its hierarchical design capability, there is no limit to the size of designs VFormal can process, provided the design has been partitioned for synthesis. VFormal verifies designs without test vectors and tests 100 percent of the design in approximately the same run time as the synthesis process.

"Formal verification is becoming more and more critical to the design process, as deep-submicron effects make design verification via simulation difficult and expensive," stated Dieter Mezger, president, COMPASS Design Automation. "Today's announcement represents COMPASS' commitment to providing designers with tools that successfully handle these effects, and we will continue to provide advanced formal verification methodologies."

New Layout vs. RTL Methodology Enabled by Laybool

Laybool, developed by SGS-Thomson, is the industry's only tool to create functional Boolean VHDL or Verilog directly from transistor netlists. Based on stable Binary Decision Diagram A binary decision diagram (BDD), like a negation normal form (NNF) or a propositional directed acyclic graph (PDAG), is a data structure that is used to represent a Boolean function.  (BDD BDD Base de Données (French: Database)
BDD Business Desktop Deployment (Microsoft)
BDD Behavior Driven Development
BDD Binary Decision Diagram
BDD Bantam Doubleday Dell
) technology, Laybool provides high performance extraction for most physical blocks, processing hundreds of thousands of transistors in only a few minutes. Additionally, Laybool offers designers automatic library model generation and verification; simulation, acceleration and emulation model creation; and provides useful input to ATPG ATPG Automatic Test Pattern Generation
ATPG Automatic Test Program Generator
 generation tools.

The combination of Laybool and VFormal provides a bridge between the systems architect and physical designer by enabling, for the first time, verification of layout directly against RTL function. This capability is key to designers using intellectual property elements, including the reuse of cores, re-engineering and retargeting of designs, by allowing designers to determine and verify the functionality of these elements.

Price and Availability

VFormal VHDL is available now. VFormal Verilog is in Beta, with production shipment scheduled for Q4 1996. U.S. pricing for VFormal is $60K for a single language (VHDL or Verilog), and $120K for the mixed-language environment. Laybool is scheduled to be available in early Q1 1997. U.S. pricing for Laybool is $95K. Both tools are available on Sun, HP and IBM (International Business Machines Corporation, Armonk, NY, www.ibm.com) The world's largest computer company. IBM's product lines include the S/390 mainframes (zSeries), AS/400 midrange business systems (iSeries), RS/6000 workstations and servers (pSeries), Intel-based servers (xSeries)  platforms.

About COMPASS Design Automation

COMPASS Design Automation is a leading provider of electronic design automation (EDA) tools and libraries for designing deep submicron application-specific integrated circuits (hardware) Application-Specific Integrated Circuit - (ASIC) An integrated circuit designed to perform a particular function by defining the interconnection of a set of basic circuit building blocks drawn from a library provided by the circuit manufacturer.  (ASICs) and application-specific standard products (ASSPs). The company supplies a complete set of tools for silicon implementation as well as front-end design and provides foundry flexible Passport(TM) and custom ASIC A redundant reference to an ASIC chip. ASICs are already customized for a specific use. See ASIC.  libraries, memory and datapath compilers, and library development tools. COMPASS is headquartered in San Jose, California San Jose (IPA: /ˌsænhoʊˈzeɪ/) is the third-largest city in California, and the tenth-largest in the United States. It is the county seat of Santa Clara County. , and develops, markets and sells its products worldwide. More information about COMPASS can be obtained on the World Wide Web by accessing http://www.compass-da.com. -0-

Note to Editors: VFormal, Laybool and Passport are trademarks of COMPASS Design Automation, Inc. All other trademarks or registered trademarks are the property of their respective owners.

CONTACT: Tsantes & Associates

Anna Leonard, 408/452-8700

anna@tsantes.com
COPYRIGHT 1996 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 1996, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Date:Sep 18, 1996
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