Compass Enables Accurate Deep Submicron Design With Multiple Drive Analyzer(TM) Tool; High Frequency Deep Submicron Designs Need Multiple Clock Drivers; New Tool Automates Analysis Process.PARIS Paris, in Greek mythology Paris or Alexander, in Greek mythology, son of Priam and Hecuba and brother of Hector. Because it was prophesied that he would cause the destruction of Troy, Paris was abandoned on Mt. , France--(BUSINESS WIRE)--March 6, 1995--Today, at the 1995 EuroASIC Conference, COMPASS Design Automation, Inc. announced its Multiple Drive Analyzer (MDA (1) (Monochrome Display Adapter) The first IBM PC monochrome video display standard for text. Due to its lack of graphics, MDA cards were often replaced with Hercules cards, which provided both text and graphics. See PC display modes and Hercules Graphics. ) tool for use in analyzing RC delays and skew (1) The misalignment of a document or punch card in the feed tray or hopper that prohibits it from being scanned or read properly. (2) In facsimile, the difference in rectangularity between the received and transmitted page. effects on complex, multi-drive clock nets typically found in high frequency ASICs. The MDA tool allows designers, for the first time, to optimize chip-level timing performance utilizing accurate clock skew In circuit design In circuit design, clock skew (sometimes timing skew) is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit) arrives at different components at different times. data. Previously, multi-drive clocks have been analyzed manually, which is time consuming, error prone and becomes a practical impossibility for nets with more than a few drivers. "For years, COMPASS has had the industry's most accurate RC delay calculation capability for single-drive nets," said Dr. Paul McLellan, vice president of technology at COMPASS. "This technology has allowed us to achieve delay accuracy within five percent of SPICE for gate level timing analysis. We were able to extend this capability to multi-drive nets by combining our extensive knowledge of the deep submicron design process with our customers' experience in designing high performance ASICs." The MDA tool allows users, following place and route, to analyze timing and skew data on large, multi-drive nets. After RC data is extracted from layout, the MDA tool then runs SPICE simulations and automatically extracts the appropriate skew data for each element on the clock net. The new delay data is automatically backannotated to the COMPASS timing database for timing verification or is output as SDF (Standard Data Format) A simple file format that uses fixed length fields. It is commonly used to transfer data between different programs. SDF Pat Smith 5 E. 12 St. Rye NY Bob Jones 200 W. Main St. Palo Alto CA Comma delimited "Pat Smith","5 E. for backannotation to Verilog(R) or other third-party simulation tools. "Deep submicron ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. designers continue to move to multi-drive clocks to reduce clock delays and skew as well as decrease system noise," said Farhad Hayat, product line marketing manager at COMPASS. "Such has been the case with all of our beta customers, one of which used the MDA tool for analysis of a 0.35 micron, 600,000-gate design that incorporated hundreds of drivers on a single clock net. The absence of an automatic analysis tool meant that designers had to spend weeks analyzing clock skews or risk having timing problems after chip fabrication fabrication (fab´rikā´sh  n),n the construction or making of a restoration. ." The Multiple Drive Analyzer tool is available now and is an option to the COMPASS Navigator(TM) Design System, which provides an advanced submicron design solution. Pricing for the MDA tool is $25,000, single user seats. COMPASS Design Automation is a leading provider of electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) tools and libraries for designing deep submicron application-specific integrated circuits (ASICs) and application-specific standard products (ASSPs). The company supplies a complete set of tools for silicon implementation as well as front-end design and provides foundry flexible Passport(TM) and custom ASIC libraries, memory and datapath compilers, and library development tools. COMPASS is headquartered in San Jose, California San Jose (IPA: /ˌsænhoʊˈzeɪ/) is the third-largest city in California, and the tenth-largest in the United States. It is the county seat of Santa Clara County. , and develops, markets and sells its products worldwide. -0- Note to Editors: Multiple Drive Analyzer, Navigator and Passport are trademarks of COMPASS Design Automation, Inc. SDF and Verilog are trademarks or registered trademarks of Open Verilog International. CDB-009 CONTACT: Tsantes & Associates Diane Orr, 408/452-8700 COMPASS Design Automation Jeff Lewis, 408/434-7909 |
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