Printer Friendly
The Free Library
19,607,059 articles and books
Member login
User name  
Password 
 
Join us Forgot password?

CompLib Graphical VHDL Generator Now Integrated with CAST Synthesizable Models.


LAS VEGAS--(BUSINESS WIRE)--June 4, 1996-- Design Automation Conference--Hantro Products Oy, Finland, today announced the integration of synthesizeable VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction.  models from CAST Inc. with Hantro's CompLib graphical VHDL generator.

CompLib combines familiar graphical design functions, automatic VHDL generators, and VHDL model libraries to help traditional FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market.  designers shift to top-down design A design technique that starts with the highest level of an idea and works its way down to the lowest level of detail. See top-down programming.

(programming) top-down design - (Or "stepwise refinement").
 using VHDL. It enables the graphical placement and interconnection of hierarchical design compoenents, and it produces standard VHDL compatible with popular simulators and synthesizers.

CompLib 1.1 now includes symbols and a selection window for SCVL-S, the Synthesizeable Standard Component VHDL Library from CAST, Inc. Users add flip flops, ALUs, counters, encoders and other SCVL-S parts to their designs by simply selecting the model from the integrated list, placing the symbol on the schematic A graphical representation of a system. It often refers to electronic circuits on a printed circuit board or in an integrated circuit (chip). See logic gate and HDL. , and graphically connecting its signals.

CompLib 1.1 is shipping now, at a suggested prioce of $1495. Other new features in this version include support for Windows 95 and NT, improved design management functions, and faster performance. Pricing for the optional CAST models varies by region.

Hantro is showing CompLib 1.1 in the CAST booth at DAC See D/A converter and discretionary access control.

DAC - Digital to Analog Converter
 (#2360). Also see Hantro's Web pages for more information and a demo (http://www.hantro.com), and see CAST's web pages for details on SCVL-S (http://www.cast-inc.com).

Since its founding in 1985, Hantro has supported advanced techniques for electronic design throughout Finland with design outsourcing, educational services, methodology consulting, and VAR distribution of key VHDL products. The company may be reached at: Hantro Products Oy, Teknologiantie 14, FIN-90570 Oulu, Finland Phone: +358-81-551 4403, Fax: +358-81-551 4490 E-Mail: Eero.Kaikkonen@hantro.pp.fi

CONTACT: Paul Lindemann,

PDL See page description language.

1. PDL - Page Description Language.
2. PDL - Program Design Language.
3. PDL - Push Down List.
4. PDL - Dave Lebling, one of the co-authors of Zork.
 Communications,

603/434-3534
COPYRIGHT 1996 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 1996, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

 Reader Opinion

Title:

Comment:



 

Article Details
Printer friendly Cite/link Email Feedback
Publication:Business Wire
Date:Jun 4, 1996
Words:275
Previous Article:Trump Indiana granted casino gaming license.
Next Article:Fancamp Acquires Gemsbok South Licence on the "KSZ".
Topics:



Related Articles
Hantro Annoucnes Complib VHDL generator; Writes VHDL from Schematics to Facilitate VHDL Entry, Simulation, and Synthesis for FPGA and System...
Speed Electronic Introduces New Option for speedCHART; Direct Drive Couples Graphical Design with HDL Simulators.
Speed Electronic adds new Flowcharting capabilities to speedCHART.
Speed INTRODUCES speedExplorer; New EDA Tool Helps Synopsys' Designers Select Optimal Synthesis Path.
CAST to release ASIC cores.
Summit introduces Visual HDL for Verilog-PC.
Sand Microelectronics Extends Its Family of Intellectual Property Analysis Tools, Introduces USB Transaction Analyzer.
CAE Plus Introduces New Versions of Its Pro-Active Virtual Prototyping Solutions for Embedded System IC Hardware/Software Development.
Casting Simulation Software. (Metalcasting Supplies).
@HDL RELEASES ENHANCED VERSION OF VERILOG DEBUGGING TOOL.

Terms of use | Copyright © 2012 Farlex, Inc. | Feedback | For webmasters | Submit articles