Columbus Interconnect Modeling Leadership Strengthened; Frequency Technology Announces Significant Performance Improvements.

SANTA CLARA, Calif.--(BUSINESS WIRE)--June 10, 1999--

Frequency Technology, Inc., the leading supplier of solutions that enable designers to accurately predict interconnect performance for deep-submicron processes, has announced that new product updates are currently in production for its industry-leading interconnect modeler, Columbus(R).

Version 2.0 of Columbus provides high-performance interconnect modeling capability for advanced deep-submicron processes and can be integrated into standard cell flows. It provides the industry's most accurate electrical descriptions for each net in a design.

With the Columbus 2.0 update, customers are seeing performance levels exceeding 200,000 nets per hour per CPU. The update combines a 10x performance improvement in standard cell flows; a hierarchical methodology to provide maximum performance for both full custom and standard cell designers; bounded accuracy for all nets; and full compatibility with leading design flows. These updates are part of the regular Columbus maintenance program.

The highest modeling performance with Columbus 2.0 is obtained by efficiently leveraging the design hierarchy. Using the new hierarchical flow, a ten-million transistor design was completely hierarchically modeled in fewer than 48 CPU-hours, a performance of more than 200,000 nets per hour. Using Columbus' distributed processing feature can significantly reduce the actual modeling time.

According to Michel Courtoy, vice president of marketing at Frequency, "Regardless of the speed, the key to design success is tight integration of the modeling in the design loop. Columbus' unique net-by-net architecture is the key to interactive interconnect modeling. This architecture enables the designer to quickly analyze the effects of small design changes such as ECOs and incremental place-and-route in a matter of minutes instead of hours or days.

"Traditional extractors process layout geometries in bulk resulting in significant run-time penalties when modeling is limited to selected nets. A tight-loop between the design and modeling tools simply cannot be established without a true net-by-net architecture in the latter."

Traditional equation-based extractors are plagued by poor accuracy on up to five percent of the nets, commonly referred to as outliers. Outliers with RC value errors of up to 50 percent have been detected; this can have a catastrophic impact on the overall performance of a chip. By removing all outlying nets, Columbus provides tightly bounded RC model accuracy, thereby eliminating compromise and insuring confidence in reaching timing closure.

A new standard cell flow for semi-custom designs provides True-3D accuracy in the Cadence, Avant!, Magma, and Monterey Design flows. This uses the latest release of LEF/DEF (5.2) and provides SPEF and DSPF outputs that are fully compatible with Pearl (Cadence) and PrimeTime (Synopsys) timing analyzers. By leveraging these flows, Columbus 2.0 performance has been improved by more than an order of magnitude.

About Frequency

Frequency Technology, Inc., based in Santa Clara, was founded in 1995 to focus exclusively on developing solutions that improve the performance of sub-quarter micron designs. Frequency's tools enable designers to accurately predict the performance of the interconnect. In 1997, the company launched Columbus(R) Interconnect Modeler, the only technology which accurately models the interconnect in deep-submicron designs, and the first of its complete family of electronic design automation tools based on the company's patented Exact Topological Decomposition algorithm.

In 1999, the company introduced Cartier(TM), the industry's first clock tree analysis solution, and Copernicus(TM), a unique solution for post-layout optimization. Frequency created the SIPPs standard for interconnect performance which is now sponsored by Si2. The company has raised venture funding from IVP, Sigma Partners, Menlo Ventures, Atlas Venture, Sofinnova and Skywood Ventures.

The company is located at Technology Station, 469 El Camino Real, Santa Clara, CA 95050. Phone: [phone]. Fax: [phone]. URL: www.frequency.com. Frequency is a member of the Cadence Design Systems (NYSE:CDN) Alanza Connections, Mentor Graphics' (Nasdaq:MENT) Open Door and Synopsys (Nasdaq:SNPS) in-Sync programs.

Note to Editors: All trademarks are the property of their respective owners.