CoWare and MIPS Technologies Win OCP-IP Outstanding Contributor of the Year Awards for 2005.
CoWare was acknowledged for contributions in the OCP-IP System Level Design Working Group. The Company made key contributions to the development of the SystemC Transaction Level Monitor (TLM) Channel version 2.1.1 and the methodology white paper, "OCP TLM for Architectural Modeling." The new features in version 2.1.1 improve model interoperability, resulting in better productivity in system level modeling.
The white paper is an influential methodology contribution to transaction level modeling. It outlines the use of the OCP TLM in the same flow with the OSCI TLM, and introduces a newly defined modeling use case, Architects View, using OCP TL2 or TL3 abstraction level for interface modeling. The white paper is accompanied with a package of SystemC code that has extensive examples for modeling in different abstraction levels, and for making models of different abstractions interoperable.
"The new transactional channel brings us even greater system-level model interoperability and reusability as a part of the OCP socket; CoWare's contribution was key to the development of the transactional models," said Anssi Haverinen, senior specialist at Nokia Technology Platforms. "It was a pleasure leading the collaboration between such productive members of OCP-IP's System-Level Design Working Group."
"We see OCP-IP's work gaining momentum with our customers, driven by the need for interoperability based on a truly open communications protocol," said A.K. Kalekos, vice president of marketing and business development at CoWare. "The leading-edge work of OCP's System-Level Design Working Group is complimented by OSCI's work on TLM, and we were happy to contribute our expertise to keep them in sync. We're delighted to be recognized for our efforts, with this award from OCP-IP."
MIPS Technologies is recognized for its work in the OCP-IP Specification Working Group, in particular for its contributions in the area of out-of-order tagging. Tagging provides the ability for interconnect and targets to re-order transactions for non-conflicting memory addresses within a single thread. Unlike threads, which enforce no ordering restrictions, tagged transactions ensure that read/write hazards are respected by the system. Tagged transactions are particularly attractive for advanced embedded CPU architectures, like the MIPS32(R) 24K(R) processor core family, which can exploit the parallelism offered by out-of-order transaction processing, but require consistent memory ordering.
"We appreciate OCP-IP's acknowledgement of our contributions to the industry. Our collaboration has enabled designers to more easily bring complex SoC designs to market quickly and efficiently," said Russ Bell, vice president of marketing at MIPS Technologies. "MIPS Technologies looks forward to future innovation with OCP-IP for improving standard interfaces and buses for the embedded market."
"OCP has a robust, thriving infrastructure driven by many independent companies providing leading-edge services and products," said Ian Mackintosh, president of OCP-IP. "We are proud of the tremendous work completed by the joint winners CoWare and MIPS, and are pleased to present them with the Outstanding Contributor Awards for 2005. We look forward to continued collaboration in the future."
For more information please visit www.ocpip.org
CoWare is the leading supplier of system-level electronic design automation (EDA) software tools and services. CoWare offers a comprehensive set of electronic system-level (ESL) tools that enable SoC developers to "differentiate by design" through the creation of system-IP including embedded processors, on-chip buses, and DSP algorithms; the architecture of optimized SoC platforms; and hardware/software co-design. The company's solutions are based on open industry standards including SystemC. CoWare's customers are major systems, semiconductor, and IP companies in the market where consumer electronics, computing, and communications converge.
About MIPS Technologies
MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and business applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers and system OEMs. MIPS Technologies and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at +1 (650) 567-5000 or www.mips.com.
The OCP International Partnership Association, Inc. (OCP-IP), formed in 2001, promotes and supports the Open Core Protocol (OCP) as the complete socket standard ensuring rapid creation and integration of interoperable virtual components. OCP-IP's Governing Steering Committee participants are: Nokia (NYSE:NOK), Texas Instruments (NYSE:TXN), STMicroelectronics (NYSE:STM), Toshiba Semiconductor Group (including Toshiba America TAEC), and Sonics. OCP-IP is a non-profit corporation delivering the first fully supported, openly licensed, core-centric protocol comprehensively fulfilling system-level integration requirements. The OCP facilitates IP core reusability and reduces design time, risk, and manufacturing costs for SoC designs. VSIA endorses the OCP socket, and OCP-IP is affiliated with VSIA. For additional background and membership information, visit www.OCPIP.org.
NOTE: MIPS, MIPS32 and 24K are trademarks or registered trademarks of MIPS Technologies, Inc. in the United States and other countries. All trademarks and service marks are the property of their respective owners.
|Printer friendly Cite/link Email Feedback|
|Date:||Sep 21, 2005|
|Previous Article:||DC Chapter of EO Releases 2005 Statistics; Members Account for Almost $1 Billion in Revenue for 2005.|
|Next Article:||PQ Media and iTVX to Publish First Global Branded Entertainment Spending and Measurement Report.|