CoWare ConvergenSC Helps MIPS Customers Beat Price/Performance Targets for Highly Competitive Designs Incorporating MIPS32 24K Cores.SAN JOSE, Calif. & MOUNTAIN VIEW, Calif. -- New Processor Support Packages for SystemC Optimize Processor Performance for DVDs, Set-top Boxes, Digital Television, and Other Performance-Critical Designs CoWare(R) Inc., the leading supplier of system-level electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) software and services, and MIPS Technologies, Inc. (Nasdaq:MIPS (Million Instructions Per Second) The execution speed of a computer. For example, .5 MIPS is 500,000 instructions per second; 100 MIPS is a hundred million instructions per second. ) announced that SystemC-based processor support packages (PSPs) for the MIPS32(R) 24K(TM) core family have been added to CoWare's extensive ConvergenSC(TM) Model Library. Together with CoWare's ConvergenSC system-level design solution, the PSPs help MIPS Technologies' customers make price/performance tradeoffs and beat their performance goals for highly competitive, complex SoC designs by allowing them to explore and debug their designs at the system level. The PSPs for the MIPS32 24K cores -- the embedded industry's highest performance 32-bit synthesizable processor cores -- are the latest in a series of models developed through an ongoing partnership between the companies. "These jointly developed PSPs -- available through CoWare -- have the speed and cycle accuracy of the latest version of the MIPSim(TM) instruction set simulator An Instruction Set Simulator (ISS) is a simulation model, usually, but by no means always, coded in a high-level language, which mimics the behavior of a mainframe or microprocessor by "reading" instructions and maintaining internal variables which represent the processor's (ISS ISS See Institutional Shareholder Services (ISS). ) combined with CoWare's powerful analysis capabilities, offering our mutual customers the best solution for their design needs," said Russ Bell, vice president of marketing at MIPS. "The PSPs will allow our OEM (Original Equipment Manufacturer) The rebranding of equipment and selling it. The term initially referred to the company that made the products (the "original" manufacturer), but eventually became widely used to refer to the organization that buys the products and customers to understand critical performance tradeoffs and the influence of embedded software early in the design cycle. This is extremely important in markets for powerful, graphical, performance-driven applications such as digital and interactive television, set-top boxes and DVDs, where meeting performance goals is critical to remaining competitive." "With the PSPs for the MIPS 24K cores, our mutual customers can now verify and modify SoC hardware and software performance before RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; , allowing them to increase performance, decrease costs and create embedded systems ideally tuned for their competitive applications," said Mark Milligan, vice president of marketing, CoWare. Designing Better Performing Systems with CoWare PSPs for the MIPS32 24K Cores The MIPS32 24K core family, which includes the 24Kc(TM), 24Kc Pro, 24Kf(TM) and 24Kf Pro versions, offers performance from 400 to 550 MHz worst case in a 0.13 micron process, the highest frequency available in 32-bit synthesizable cores for embedded markets, while minimizing design time and reducing product costs. By running simulations in ConvergenSC -- which speeds the concurrent design of SoCs with embedded software by combining hardware/software partitioning, platform assembly, simulation, debug and analysis capabilities--together with the CoWare PSPs, users can quickly determine the optimum architecture for their specific application and debug their software and hardware early in the design process. The tools let customers perform detailed analysis of processor throughput and latency, as well as memory subsystem performance and bus analysis. Analysis results can be viewed graphically and used to determine how a design should be refined. With the ability to measure the key parameters that affect the performance of the processor in their design, users can design better performing systems optimized around the MIPS32 24K cores. The new PSPs are also integrated with the debugger in CoWare's LISATek(TM) product -- a fully integrated solution for embedded processor modeling, design, and software tool generation. This adds full embedded software debug capabilities such as source and assembly level debug, viewing and tracing memory and internal registers, and complete control of the core. The new CoWare PSPs are compatible with the MIPS Software Toolkit, including the MIPS SDE SDE - Software Development Environment: equivalent to SEE. software tool chain (compiler, assembler, and linker) for the processor. The PSPs are cycle accurate, supporting MIPS features such as an 8-stage pipeline, configurable instruction and data cache, MMU (Memory Management Unit) The part of the computer that governs memory access. Either part of the CPU chip or housed on separate chips, the MMU controls memory partitions and virtual memory. See memory and virtual memory. MMU - Memory Management Unit configurable dual-entry joint TLB and OCP (processor) OCP - Order Code Processor. on-bus interconnect. Pricing and Availability CoWare's PSPs for the MIPS32 24K core family will be available in production release in Q3 2004. For pricing information, contact your local sales office or email sales@coware.com. For more information on the PSPs for the MIPS32 24K cores, and other models in the ConvergenSC Model Library, visit www.coware.com. About MIPS Technologies MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and business applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC RISC in full Reduced Instruction Set Computing Computer architecture that uses a limited number of instructions. RISC became popular in microprocessors in the 1980s. solutions. The company licenses its intellectual property to semiconductor companies, ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. developers and system OEMs. MIPS Technologies and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at 650-567-5000 or www.mips.com. About CoWare CoWare is the leading supplier of system-level electronic design automation (EDA) software tools and services. CoWare offers a comprehensive set of electronic system-level (ESL) tools that enable SoC developers to "differentiate by design" through the creation of system-IP including embedded processors, on-chip buses, and DSP algorithms; the architecture of optimized SoC platforms; and hardware/software co-design. The company's solutions are based on open industry standards including SystemC. CoWare's customers are major systems, semiconductor, and IP companies in the market where consumer electronics, computing, and communications converge. CoWare's corporate investors include ARM Ltd. ((LSE LSE - Language Sensitive Editor :ARM); (Nasdaq:ARMHY)), Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services. http://cadence.com/. See also Verilog. (NYSE NYSE See: New York Stock Exchange :CDN (Content Delivery Network) A system of distributed content on a large intranet or the public Internet in which copies of content are replicated and cached throughout the network. ), ST Microelectronics (NYSE:STM (Scanning Tunneling Microscope) A microscope that can image down to the atomic level. An STM uses a piezoelectric tube with a tiny sharp tip at the end that is moved within nanometers of the object being sampled. ), and Sony Corporation (NYSE:SNE). CoWare is headquartered in San Jose, Calif., and has offices around the world. For more information about CoWare and its products and services, visit http://www.coware.com. ConvergenSC and LISATek are trademarks of CoWare, Inc. CoWare is a registered trademark of CoWare, Inc. in the United States. All other trademarks are the property of their respective owners. MIPS, MIPS32, MIPS-Based, 24K, 24Kc, and 24Kf are trademarks or registered trademarks of MIPS Technologies, Inc. in the United States and other countries. |
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