Co-Design Automation & Real Intent Steer Industry-Wide Convergence On Assertions Through Accellera Donation.

Business/Technology Editors

SAN JOSE, Calif.--(BUSINESS WIRE)--March 11, 2002

International HDL Conference--

Verilog-Based SUPERLOG Assertion Language Driven By Multiple

Verification Companies

Co-Design Automation, Inc., a provider of electronic system simulation, and Real Intent, Inc., a provider of formal functional verification systems today donated the SUPERLOG(R) Design Assertions language Subset to the standards organization Accellera. The goal is to bring an industry-wide convergence on an efficient assertion language.

The Co-Design/Real Intent SUPERLOG Design Assertions Subset (DAS) will enable designers and verification engineers to write design checks using a standard language that can be applied to a broad range of tools without modification, improving verification productivity. It allows the efficient description of design assertions using a recognizable Verilog hardware description language (HDL)-based syntax, simplifying a range of applications.

The donation includes automated verification capabilities embedded within Co-Design Automation's Systemsim(TM) system simulator, as well as formal model checking semantics contributed by Real Intent, derived from its Verix(TM) product line.

"Our combined extensive technical and customer experience in formal verification and simulation has allowed us to represent the customer perspective. Together with our partners, we have actively worked to design a unique assertion framework that addresses their needs," notes Dr. Prakash Narain, president and chief executive officer (CEO) of Real Intent. "This assertion standard enables a unified simulation and functional formal verification methodology which promises significant improvements in design verification throughput."

Other EDA vendors, including 0-In Design Automation, Inc., Novas Software, Inc. and Verplex Systems, Inc., also contributed time and resources to defining the SUPERLOG DAS, enabling its application across a broad range of verification technologies. The donation was further endorsed by verification companies Axis Systems, Inc., SynaptiCAD, Inc., Tharas Systems, Inc., and Veritable, Inc.

"The time is right to establish an assertions standard usable by designers and verification engineers that may be applied throughout the design flow, and across a range of EDA tools," says Simon Davidmann, Co-Design's CEO. "Our expertise in the simulation and verification space, together with that of our partners, has enabled a rich and powerful verification mechanism that dramatically reduces the time taken to establish correct design operation."

Dennis Brophy, chairman of Accellera and director of strategic business development at Model Technology, a Mentor Graphics (NASDAQ: MENT) company, agrees. "Many designers have started to utilize assertions in a wide range of tools; there is a clear need for an industry-wide standard in this area. Accellera addresses this need head-on and the donation of the Design Assertions Subset, driven by multiple companies, accelerates the creation of this standard."

For more details on Co-Design's standardization activities, contact Dave Kelf, Co-Design's vice president of marketing. He can be reached via email at [e-mail] or at (877) 6 CODESIGN, Ext. 404.

About Real Intent

Real Intent, headquartered in San Jose, California, offers award-winning formal functional verification products for electronic design. These products give users the capability of comprehensively verifying designs early and significantly reduce the cost of verifying integrated circuits, electronic systems and systems on a chip. Real Intent is located at 3910 Freedom Circle, Suite 102A, Santa Clara, CA 95054, tel.: [phone], fax: [phone], email: [e-mail], web: http://www.realintent.com.

About Co-Design Automation

Co-Design Automation is an EDA company focused on advanced simulation products for large-scale system designs. It is privately held and funded by investors from within the EDA developer and user communities, including Intel Capital Corporation and Redwood Venture Partners, Inc. The staff includes notable simulation experts Phil Moorby, creator of the Verilog HDL and the first fellow at Cadence Design Systems, Inc. (NASDAQ: CDN), and Peter Flake, creator of the HILO HDL. In 1999, Co-Design announced the SUPERLOG system design language, now utilized by 12 partner companies. Its products -- SYSTEMSIM and SYSTEMEX -- are achieving success throughout the electronics industry worldwide in system platform and advanced verification applications. Corporate headquarters is in Los Altos, Calif. Telephone: (877) 6 CODESIGN. Facsimile: [phone]. Email: [e-mail]. On-line information is found at its Web Sites: http://www.co-design.com and http://www.superlog.org.

Verix and Real Intent are trademarks of Real Intent. SUPERLOG is a registered trademark and SYSTEMSIM, SYSTEMEX, CBlend are trademarks of Co-Design Automation, Inc. Verilog is a trademark of Cadence Design Systems, Inc. Co-Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.