ClearSpeed Demonstrates Massively-Dense Computing with TeraFLOP Performance and Enhanced Software Tools for Easier Programming of Accelerated Multi-Core Systems.

Unique Software Capability and the ClearSpeed Developer Community Program Pave the Way to Unleashing the Performance of Energy-Efficient, Accelerated, Industry-Standard Clusters

SAN FRANCISCO -- ClearSpeed Technology (LSE:CSD), the world leader in acceleration for high performance computing (HPC), today announced new benchmark results that prove the potential for massively-dense, energy-efficient systems based upon accelerated Intel[R] Multi-core architectures; enhanced software tools for easier programming of accelerated heterogeneous systems; the introduction of the ClearSpeed Developer Community Program; and a specially-priced Developer Bundle.

Demonstrating the potential of heterogeneous multi-core systems, a ClearSpeed accelerated dual core Intel[R]-based cluster recently delivered over one TeraFLOP of LINPACK performance while occupying just 16u of rack space. With each ClearSpeed Advance e620 accelerator delivering 80 GigaFLOPS peak double precision performance and over one GigaFLOP per watt of sustained LINPACK performance, the entire cluster had a maximum power consumption of less than 7KW and completed the benchmark in just 14 minutes, half the time required by the non-accelerated system. The energy used to achieve this TeraFLOP performance was approximately 1.5KWh, costing a mere 15 cents assuming a cost of 10 cents per KWh. With the latest quad core Intel processors, the same performance and energy profile could be compressed into just 10 rack units and cost less than $150,000. To underscore what a difference a decade makes, in 1997 Intel impressed the industry with the world's first-ever terascale system known as ASCI Red that was delivered to Sandia National Laboratories. With 4,510 compute nodes the then state-of-the-art and record-breaking system occupied 2,500 square feet, consumed 850KW and cost $55 million.

"The massively-dense, energy-efficient systems that can be built with ClearSpeed accelerators are essential to providing the orders of magnitude greater compute power required to tackle the next level of grand challenge problems, such as modeling protein interactions or simulating turbulent airflow for aero engine design," said Ben Bennett, ClearSpeed general manager. "Even more important than the accelerators themselves, making the software development environment easy and familiar is the single most critical element in realizing the performance of accelerated multi-core systems. ClearSpeed has established a significant lead in this area."

Building upon its breakthrough performance, ClearSpeed has enhanced the functionality of its CSXL software library to provide plug and play acceleration for the most commonly used 64bit level 3 BLAS and LAPACK functions that underpin the foundations of the vast majority of scientific and engineering applications. ClearSpeed is unique in its ability to accelerate applications based on standard libraries without requiring any modification to the application code.

"The availability of standard software libraries that connect to accelerators is important for the adoption of accelerators alongside today's multi-core systems," said Lorie Wigle, director of Technology Initiatives and Software Strategy for Intel's Server Platform Group. "The ClearSpeed CSXL software library is an important step towards alleviating the software developers' adoption of accelerators in Intel[R] Multi-Core systems."

For developers wishing to adapt their application codes to take full advantage of accelerated multi-core architectures, ClearSpeed's software development environment provides the only visual debugging and profiling capabilities for analyzing the entire system. The tools allow developers to visually inspect all aspects of their application code - from the host code running on an x86 multi-core platform to the scheduling of instructions executing on the ClearSpeed Advance accelerator's CSX600 coprocessors and the associated interaction across the I/O bus.

With the combination of its energy-efficient performance capabilities and industry-leading software tools paving the way, ClearSpeed has announced the creation of a software developer community. ClearSpeed's software developer community will provide a forum for developers to collaborate and share their expertise in developing code that exploits heterogeneous, accelerated multi-core architectures. Designed for developers working on compute-intensive HPC applications that benefit from parallel execution, members of this community will have access to a developer website, forums, technical updates, early access to new software releases, user group events and discounts. To join as founding members, developers are encouraged to sign up at developer.clearspeed.com.

"The programming environment is the biggest obstacle to developing parallel code for multi-core processors and accelerated systems," stated Matt Fyles, team leader for ClearSpeed software development tools. "The ClearSpeed visual tools are the only products available today that have been specifically designed for improving the development of software running in multi-core heterogeneous systems; the tools provide far greater insight into debugging and tuning than any other development environment available now or in the foreseeable future."

In conjunction with the build-out of the ClearSpeed Developer Community, a specially-priced, limited-time offer developer bundle has been introduced, which includes a ClearSpeed Advance e620 Accelerator (ClearSpeed's PCIe solution), the ClearSpeed Software Development Kit (SDK) and 12 months support. The Advance e620 bundle will allow developers to benefit from ClearSpeed's industry-leading performance per watt by accelerating their applications by 10x or more.

ClearSpeed at IDF 

ClearSpeed has two booths at IDF located at #529 in the I/O Accelerator Community and #120 in the IHV community, where developers will be able to view demonstrations of ClearSpeed's software tools and accelerated Amber, a popular life science application. ClearSpeed will also be present at Intel's booth #728 in the I/O community, where Intel will be demonstrating a proof of concept advanced research prototype for direct programming of heterogeneous systems consisting of Intel[R] Multi-Core systems and heterogeneous accelerators. ClearSpeed solutions will be highlighted along with Intel accelerator solutions to demonstrate the proof of concept heterogeneous direct programming environment. Additionally, developers are invited to industry panel sessions focusing on Acceleration technology for HPC:

* Tuesday, September 18, 10:00-10:50 a.m. - John Gustafson, ClearSpeed CTO of HPC, on a panel titled "Emerging Technologies for HPC"

* Wednesday, September 19, 1:30-3:20 p.m. - Ray McConnell, ClearSpeed CTO, on a panel titled "Trends and challenges ahead for accelerator usage and growth"

About the ClearSpeed Developer Bundle

The Advance e620 Developer Bundle is being offered on a one-time basis at a price of $5,295 and is only available to developers. It consists of one Advance e620, the ClearSpeed SDK, 12-month support including single-user login to support.clearspeed.com, access to customer support hotline for up to two cases and standard documentation. Only one bundle may be purchased per project or department and standard ClearSpeed terms and conditions apply. To order visit www.clearspeed.com.

About ClearSpeed

ClearSpeed Technology is a semiconductor company that develops massively parallel coprocessors and accelerator boards delivering unmatched performance per watt for high performance computing applications on industry-standard systems. ClearSpeed has offices in San Jose, California, and Bristol, UK, and has over 50 patents granted with additional pending. For more information, visit www.clearspeed.com.