ClearSpeed(TM) Applauds the Geneseo Initiative for Acceleration Technology.Proposed Extensions to PCIe Specification Promise Ease of Use and Efficiency Improvements SAN FRANCISCO San Francisco (săn frănsĭs`kō), city (1990 pop. 723,959), coextensive with San Francisco co., W Calif., on the tip of a peninsula between the Pacific Ocean and San Francisco Bay, which are connected by the strait known as the Golden -- ClearSpeed Technology (LSE LSE - Language Sensitive Editor : CSD CSD Commission on Sustainable Development CSD Serbian Dinar (ISO currency code) CSD Christopher Street Day CSD Circuit Switched Data (Sprint) CSD Computer Science Department CSD Community School District ), the only supplier of coprocessor coprocessor Additional processor used in some personal computers to perform specialized tasks such as extensive arithmetic calculations or processing of graphical displays. acceleration technology exclusively focused on the high precision, high performance and low power requirements of the high performance and technical computing market, today announced its support for the Geneseo technology proposal to extend the PCI Express A high-speed peripheral interconnect from Intel introduced in 2002. Note that although sometimes abbreviated "PCX," PCI Express is not the same as "PCI-X" (see PCI-SIG and PCI-X for comparison). As a result of the confusion, "PCI-E" or "PCIe" is the accepted abbreviation. specification to address the needs of application acceleration. Despite impressive advances in microprocessor technology such as the Dual-Core Intel[R] Xeon[R] Processor 5100 Series, a tradeoff still persists between designing a computer for the full range of applications and designing it for technical applications that make heavy use of floating-point arithmetic. The Geneseo proposal both endorses the role that acceleration technologies have to play and recognizes that there is a degree of processor to accelerator interaction that is inefficient under the current PCIe model. "We're always excited by improvements to the PCIe architecture to deliver better performance and functionality, but that's not the main benefit here," said Simon McIntosh-Smith, vice president of applications for ClearSpeed Technology. "The Geneseo proposal goes to the heart of the software programming model and has the potential to make accelerator technologies much more efficient and easier to use than they are with the current generation of PCIe." Both the current and next generation of PCI Express have been designed and optimized primarily for graphics and advanced I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output applications. The needs of application accelerators that complement general purpose processors by providing optimized processing for very specific applications and algorithms were not considered when the current specifications were agreed. The Geneseo proposal is a set of extensions to PCIe hardware and software architecture intended to improve platform performance in the application accelerator environment through four areas of enhancement: * New semantics for reduced signaling and synchronization overhead * Improving speed and efficiency of access to memory through new semantics and traffic management * Transaction ordering attributes to optimize ordering in memory hierarchy The levels of memory in a computer. From fastest to slowest speed, they are: 1. CPU registers 2. L1 cache 3. L2 cache 4. Main memory 5. Virtual memory 6. Disk * Dynamic frequency or voltage-imposed performance and power operational modes These enhancements will enable Geneseo accelerators to: * use the existing PCIe architecture to initialize To start anew, which typically involves clearing all or some part of memory or disk. and manage devices, * streamline application-to-accelerator interactions * reduce system and software latency and overhead "We have been very impressed with the approach to Geneseo," said Ray McConnell, chief technology officer for ClearSpeed Technology. "Intel has played a leadership role in bringing the community together to collaborate on a process to deliver an open standard that will advance the adoption of acceleration technology benefiting users and vendors alike." ClearSpeed Exhibits and Presentations at IDF (Intermediate Distribution Frame) A wiring rack located between the MDF (main distribution frame) and the intended end user devices (telephones, routers, PCs, etc.). Cables run from the outside world to the MDF and then to the IDFs. See MDF and wiring rack. ClearSpeed will be exhibiting in the PCIe community (booth number 327) where it will preview a demonstration of its PCIe accelerator board and also in Intel's IHV (Independent Hardware Vendor) An organization that makes electronic equipment. It implies a company that specializes in a niche area, such as display adapters or disk controllers, rather than a computer systems manufacturer. Contrast with ISV. community (booth number 323) where it will demonstrate the record breaking ClearSpeed acceleration of a Dual-Core Intel[R] Xeon[R] 5100 series processor-based system. In addition there will be several opportunities to attend ClearSpeed presentations. ClearSpeed's vice president of applications, Simon McIntosh-Smith, will participate in an industry press panel on Wednesday morning to discuss the Geneseo initiative. John Gustafson, ClearSpeed's CTO (Chief Technical Officer) The executive responsible for the technical direction of an organization. See CIO and salary survey. of High Performance Computing will represent ClearSpeed on a panel discussing "The Rocky Road to Petaflop Computing" on Wednesday, September 27 from 10:00-10:50 a.m. in Room 2011. About ClearSpeed ClearSpeed Technology is a specialist semiconductor company focused on delivering high-performance coprocessors to be used alongside general purpose processors in the world's most compute-intensive applications. ClearSpeed's advanced multi-threaded array processing technology provides the ability to significantly accelerate data-intensive applications at extremely low power. Products include chips, boards, software tools, applications and support. ClearSpeed has offices in San Jose, Calif. and Bristol, UK and has 84 patents granted and pending. For more information on ClearSpeed, visit www.clearspeed.com. About the Intel Developer Forum Intel Developer Forum (IDF), is a twice yearly gathering of technologists to discuss Intel products and products based around Intel products. The first IDF was in 1997. There is usually a Spring IDF and a Fall IDF. In its 10th year, IDF is the premier global technology forum for hardware and software developers to confer on Intel-based platforms, technologies and solutions, and the new usage models they enable. Visit www.intel.com/idf for more information. |
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