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Clear Logic Awarded Patent On Bitstream-based ASIC Conversion Technology.


Business Editors/High-Tech Writers

SAN JOSE San Jose, city, United States
San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850.
, Calif.--(BUSINESS WIRE)--Nov. 7, 2001

Clear Logic(R) today announced that it has been awarded a patent on its bitstream-based ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor.  conversion technology. US Patent 6,311,316, issued on October 30, 2001, protects Clear Logic's method of creating an ASIC using the bitstream from a programmable logic device See PLD. .

In view of Altera's recent announcement of its HardCopy(SM) technology, Clear Logic today notified Altera of the existence of the patent and sent a copy of the patent to Altera for review.

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 Don Knowlton, Clear Logic's marketing vice president, "It looks to us like HardCopy may be similar to Clear Logic's proprietary and patented technology because both use information from bitstreams for the FPGA-to-ASIC conversion process. We have given Altera a copy of our patent for review and look forward to their response.

"We invented this technology over five years ago and have been using it since 1998. During that time we have created over 1,700 ASICs without charging customers for NRE (Non-Recurring Engineering) Refers to the cost of creating a new product, which is paid up front. Contrast with "production cost," which is ongoing and based on the quantity of material produced. ," Knowlton added.

The technology covered by Clear Logic's patent was originally developed in 1996 and is currently being used for its PLD (Programmable Logic Device) Refers to a variety of logic chips that are programmable at the customer's site, the customer being the vendor of the finished chip, not the end user.  replacements and Liberator(TM) ASICs. Clear Logic's LPLD LPLD Lawrenceburg Public Library District (Lawrenceburg, Indiana)
LPLD Lawyers for People with Learning Disabilities
(R)s (Link Processed Logic Devices) support the use of Altera MAX(R) 7000 PLDs as prototyping media. The company's Liberator ASICs support the use of FLEX 10K FPGAs as ASIC prototypes. Clear Logic's ClearShot(R) technology, covered by the patent, is used to extract the customer's proprietary design information from the bitstream file to create instructions that are used to configure the company's ASIC devices. Clear Logic's NoFault(R) test generation software, also covered by the patent, uses scan registers to obtain 100% fault coverage, based on the customer's design. Clear Logic devices have die sizes that are as much as 60% smaller than the programmable prototypes and cost as much as 70% less.

Clear Logic employs proprietary software that converts the programming file from an Altera CPLD (Complex PLD) A programmable logic device that is made up of several simple PLDs (SPLDs) with a programmable switching matrix in between the logic blocks. CPLDs typically use EEPROM, flash memory or SRAM to hold the logic design interconnections. See PLD and SPLD.  prototype to a laser-processed logic device. There are no NRE charges or minimum order sizes. Clear Logic devices arrive at the customer's site ready to plug in the socket. These devices are functionally identical to their CPLD counterparts. Clear Logic's World Wide Web site is www.clear-logic.com.

Note to Editors: Clear Logic, ClearShot, NoFault and LPLD are registered trademarks of Clear Logic. Liberator is a trademark of Clear Logic. Altera, FLEX and MAX are registered trademarks of Altera Corporation. HardCopy is a service mark of Altera Corporation
COPYRIGHT 2001 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2001, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Date:Nov 7, 2001
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