Clear Logic's Robust Simulation Models Provide Comprehensive Timing Data for FPGA-prototyped ASIC Designs.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Nov. 20, 2000

Design-specific Simulation Models, Available Over the Internet,

Let Designers Ensure Correct Timing for Clear Logic(R) ASICs

Clear Logic, Inc. today announced a comprehensive web-based capability to provide simulation models for its CL10K family of link-configured ASICs. Designers of Clear Logic ASICs use programmable FPGAs from Altera(R) for prototyping, dramatically reducing ASIC development costs and time-to-market. Clear Logic migrates the bitstream from the prototype FPGA directly to the company's ASIC without any modification, redesign or "conversion." Migration is done by Clear Logic, at its factory. The resulting ASICs operate identically to the FPGA prototype in the same socket. The simulation models being introduced today provide much more complete timing and hierarchy information than those provided by the tools from the FPGA manufacturer. The Clear Logic simulation models allow designers a much broader range of options for identifying and solving timing problems.

According to Don Knowlton, Clear Logic's vice president of marketing, "ASIC designers expect to simulate their designs very thoroughly to ensure functionality and timing. Since Altera FPGAs are used to prototype Clear Logic ASICs, designers have been forced to rely on FPGA simulation models generated by Altera's FPGA design tools. However, we were appalled by the lack of complete timing information in these models. They provide only worst cases for propagation delay, and set-up and hold timing. If variations in operating temperature, power supply voltage, or the silicon manufacturing process cause the device to operate with shorter delays than the worst cases, the design could fail in an actual operating environment, even though it simulated successfully using the FPGA models. For example, a pulse that appears wide enough in the simulation done using the models from the FPGA vendor may be too short when the system operating environment varies. In the case of a pulse generated to control writing to a memory, the data stored in the memory would be corrupted, potentially causing catastrophic system failure.

"Another weakness of the Altera models is that they remove most of the design hierarchy, presenting an essentially flat model of AND, OR, NAND and XOR gates that is virtually impossible to trace back to the original schematic or to the physical implementation in the FPGA's coarse grained logic elements. As a result there is really no practical way for a designer to trace the actual signal routing to determine what options are available to correct a timing error uncovered in the simulation.

"In order to give our customers maximum control over their designs, Clear Logic has developed its own simulation models for Clear Logic ASICs. Clear Logic's models are based on the customers' bitstream. However, unlike the models provided by Altera, Clear Logic's simulation models preserve the design's hierarchy and also provide comprehensive information on minimum, typical and maximum delays for each internal circuit. These models give designers the power to accurately simulate their design and to explore alternatives that can radically improve performance or design margins," Knowlton added.

Allows Identification of Problems Associates With Short Pulse Widths -- Since designers are usually trying to squeeze the maximum performance out of their designs, minimum delays might not seem that important. However, a pulse that is wide enough at the maximum delay may be too narrow if environmental conditions or variations in the process result in minimum or even typical delays. A pulse width that is too short could result in an inability to write to memory correctly.

Since the Clear Logic models include typical and minimum parameter values, as well as maximum specifications, designers can run corner simulations to identify problems that cannot be found using a single corner model.

Allows Designers to Evaluate Other Options -- Clear Logic models provide designers with information that may allow them to simply restrict the operating environment, if a corner simulation indicates a design failure. Using the models available with Altera FPGAs, there is no way of evaluating whether or not the circuit design can be preserved by simply providing less variation in the voltage or temperature operating ranges. If the designer has the option of tighter control of the voltage or temperature environment in which the end product will be used, it might be possible to work with a circuit that fails in a particular corner in the standard operating range. Clear Logic models provide the information the designer needs to make these tradeoffs in particularly difficult designs.

Helps Designer Locate the Source of the Problem on the Device Layout -- In contrast to overly simplified FPGA models that flatten the design to the gate level, Clear Logic's simulation models preserve the hierarchy in the design, so the designer can physically locate where on the ASIC the problem occurs. Models generated by tools from Altera offer no information about placement or routing that could be used to resolve the timing problem. Clear Logic models indicate for each signal, the side of the chip the circuit is on, the row and column in which the circuit resides and which one of the logic elements or SRAM embedded array blocks (EABs) contains the signal. Using this information, the designer can go back to the original schematic and identify the precise location of the timing problem. In many cases, manual routing may be enough to get the design within its timing constraints. For example one circuit may have sufficient margin in its timing that it can be routed along a longer path, freeing up the routing resources for a second circuit having a more critical path. Clear Logic simulation models provide the complete information needed to evaluate routing and floor planning tradeoffs.

Models Work With All Third-party Verilog(R) Simulation Tools -- Clear Logic's simulation models work with all third-party Verilog simulation tools, including Synopsys(TM)' VCS and Cadence(R)'s Verilog XL. In addition, many board level VHDL simulators will directly accept Clear Logic's Verilog models as blocks in their overall simulation.

Verilog Models Delivered Within 24 Hours Over the Internet -- Clear Logic currently provides simulation models for its CL10K ASICs in the Verilog language. As part of Clear Logic's design migration process, the Verilog models are generated by Clear Logic, based on the bitstream that the designer submits to Clear Logic's web site. They are returned to the designer, by email, within 24 hours. Since Clear Logic generates the models for the customer, there is no need to purchase any additional EDA tools or to purchase software upgrades to support newer devices, as is the case when using models from FPGA vendors. Clear Logic does not charge for the models. Free samples of Clear Logic ASICs are shipped within two to three weeks of receipt of the customer's first article request, including the final version of the bitstream.

VHDL models for Clear Logic designs will be available during 2001.

Clear Logic employs proprietary software that converts the bitstream file from an Altera FPGA prototype to a link-configured ASIC device. Clear Logic has no NRE charges or minimum order sizes. Clear Logic devices arrive at the customer's site fully pre-configured and ready to plug in the socket. Clear Logic devices are guaranteed to function identically to their FPGA prototype counterparts. Clear Logic's World Wide Web site is www.clear-logic.com.

Note to Editors: Clear Logic is a registered trademark of Clear Logic. Altera, MAX+PLUS and FLEX are registered trademarks of Altera Corporation. Synopsys is a trademark of Synopsys Corporation. Cadence and Verilog are registered of Cadence Design Systems, Inc.