Clear Logic's No-NRE Liberator ASICs From FPGA Prototypes in Five Weeks; Low Unit Prices & Power Consumption, No-NRE, & Five Week Turn Around.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Sept. 17, 2001

Clear Logic(R) today announced the availability of production quantities of the first member of its Liberator(TM) ASIC family. The 50,000 gate Liberator CL10K50V is the world's first device to offer customers the low unit costs and power consumption of masked-ASICs with the quick turn-around, flexibility, and low NRE of an FPGA-based design flow.

The Liberator CL10K50V ASIC is prototyped using a re-programmable FLEX 10K50V FPGA and standard third-party FPGA design tools. Since the prototype is re-programmable, designers may iterate the design as many times as desired with no extra costs. The FPGA is the final prototype; there is no foundry prototyping, and the only prototyping cost is the cost of the FPGA.

Internet-based ASIC Creation -- Liberator ASICs are created entirely over the Internet with no design "conversion" and no customer-side engineering. The designer simply submits the FPGA prototype bitstream to Clear Logic's Web site, www.clear-logic.com, and Clear Logic migrates the FPGA prototype bitstream directly to the Liberator architecture, using its proprietary ClearShot(R) bitstream migration software. Clear Logic generates simulation models, device configuration instructions, and test vectors with 100% fault coverage, based on the bitstream. The simulation models are sent to the engineer within 24 hours of receiving the bitstream. Free configured sample devices are shipped within four to five weeks. Production volumes are shipped within five to six weeks of receiving an order.

According to Don Knowlton, Clear Logic's vice president of marketing, "Today, plenty of ASIC designs are prototyped using FPGAs. However, when it's time to go into production, there is a complicated conversion process that essentially requires a complete redesign. Once complete, the new design goes to the ASIC vendor for masks and a prototype. Using a five-layer, 0.35 micron process, mask charges will run about $25,000 to $100,000. If there is a mistake in the prototype, the cost of new masks will be repeated. And the minimum order quantity can be huge!

"Many products don't have the volumes required by ASIC vendors," Knowlton explained. "Others require the flexibility to accommodate rapidly changing standards with design modification. Our Liberator ASICs are ideal for these designs. They offer FPGA flexibility, quick design turnaround and low fabrication costs, with ASIC pricing and power consumption. Since we have no minimum orders, customers can order ten thousand units and, if the design changes later, order another ten thousand units with the new configuration -- just as they would with an FPGA.

"If a customer could order as few as 10,000 ASIC units, the amortization of the $50,000 in mask charges, adds $5 to what would be an $8 to $10 part, for a total unit cost of $13 to $15. With a price of about $15 each in volume, our Liberator ASICs are at parity with ASICs, but without the risks or lengthy fabrication cycles."

Accurate Simulation Models -- ASIC vendors, including Clear Logic, provide simulation models that cover all process corners, so the designer can verify the design thoroughly prior to going to silicon. Vendors of the FPGAs that are used to prototype Liberator ASICs provide models that cover only worst case, slow corner parameters. If variations in operating temperature, power supply voltage, or the silicon manufacturing process cause the device to operate with shorter delays than the worst cases, the design could fail in its operating environment, even though it simulated successfully using the FPGA models. For example, a pulse to control a write to memory that appears wide enough in the simulation, may be too short when the system operating environment varies, causing the data to be corrupted.

Clear Logic's Liberator simulation models provide comprehensive information on minimum, typical and maximum delays for each internal circuit. They also preserve the design's hierarchy, so errors are easy to find and designers can explore alternatives that can radically improve performance or design margins.

Automatic Test Vector Generation With 100% Fault Coverage -- ASIC test vector generation can take as much as 40% of the design cycle. Unlike any other ASIC available today, Clear Logic's Liberator ASICs automate the test vector generation process and guarantee 100% fault coverage. Scan registers embedded on the ASIC provide testability through the chip I/O when a special test mode is activated. The test vectors are based on the customer's specific bitstream, and test the unique logic configuration of that design. This capability radically simplifies the testing of difficult to test logic implementations, such as long chains of counters.

Clear Logic tests every Liberator ASIC at the factory twice -- on the wafer and after packaging. Absolutely no customer effort or cost is required for any aspect of the test process.

Altera(R) (Nasdaq:ALTR) FLEX 10KA Prototypes Support Liberator Architecture -- Liberator ASICs are the only ASICs that can directly accept FPGA bitstreams without any "conversion." This ability to accept an FPGA bitstream is due to the fact that the FPGA prototypes have the same type of logic structures as Liberator ASICs and can perform the same functionality, including pin-outs and internal timing. Rather than using simple gates as the logic unit, Liberator CL10K50V ASICs have logic units that include a four-input lookup table with a register. The logic units are arranged in eight unit blocks (called logic building blocks or LBBs) with local interconnect between them. Every row of LBBs has a 2 Kbit block of embedded SRAM. The LBBs, SRAM and I/O are connected by high-speed global interconnect.

The FLEX 10K50V FPGA that is used as the Liberator's prototyping medium has similar logic structures that support essentially identical functionality. When configured with the same bitstream, the two types of devices are literally interchangeable in the same socket.

Enables Four to Five Week Turn Around -- Unlike conventional ASICs with multiple masks and lengthy fabrication cycles, Liberator ASICs are configured by severing vertical links in the interconnect that run through vias in the die. Link-configuration is the last step in the fabrication process, so Liberator ASICs have product turnaround cycles of four to five weeks for samples and five to six weeks for production quantities. Historically, many designs have been kept in FPGAs for production because standards are continually evolving or product life cycles are too short. These designs have had no cost reduction path. Since the turnaround for a Liberator ASIC is very quick, designs that were previously locked to FPGAs can take advantage of low ASIC prices and power consumption. Since there are no minimum orders for Liberator ASICs, there is no risk of obsolete inventories. Since there are no masks, there are no costly NRE charges.

Vertical Link Configuration Technology Eliminates Transistors -- The vertical link technology is the key to Clear Logic's ability to offer FPGA-like functionality at ASIC prices. User-programmable FPGAs use hundreds of thousands of transistors to implement their programmability. For example, FLEX 10K FPGAs use six transistors per configuration element. This silicon-intensive user programmability is invaluable during development and prototyping, but it is not necessary for production devices. In fact, programmability just adds cost in a production situation.

Clear Logic's Liberator ASICs do not need to be field programmable, so they do not need those transistors. A single Liberator configuration element consists of a single vertical link that takes up only 2.50 um2 of silicon area -- 97% less silicon than a FLEX configuration element on the same process technology. Altogether Clear Logic's Liberator CL10K50V uses a million fewer transistors than its FLEX prototype and has a 60% smaller die size.

Lower Power Consumption -- The much smaller number of transistors in Liberator CL10K50V ASICs result in substantially lower power consumption when compared to an FPGA implementation. Designs done in Liberator ASICs typically consume 30% less power than an FPGA.

Packaging, Pricing and Availability -- The 50,000 gate Liberator CL10K50V is available now in production quantities in 240-pin PQFP, 240-pin RQFP, and 356-pin (ball) BGA packages -- all pin compatible with comparable FLEX 10K50V packages. Sample configured devices are free of charge. Production quantities are priced as low as $14.80 (CL10K50VQC240-3) in quantities of 50,000 units.

Clear Logic employs proprietary software that converts the programming file from an Altera FPGA prototype to a laser-processed logic device. Clear Logic has no NRE charges or minimum order sizes. Clear Logic devices arrive at the customer's site fully pre-configured and ready to plug in the socket. Clear Logic devices are guaranteed to function identically to their FPGA counterparts. Clear Logic's World Wide Web site is www.clear-logic.com.

Note to Editors: Clear Logic, LPLD, and NoFault are registered trademarks of Clear Logic. Liberator is a trademark of Clear Logic. Altera and FLEX are registered trademarks of Altera Corporation.