Cirrus Logic Unveils New Unified Memory Architecture GUI Accelerator; Delivers Standard Graphics Performance at Significant Cost Savings.FREMONT, Calif.--(BUSINESS WIRE)--March 8, 1996--Cirrus Logic Inc. (NASDAQ NASDAQ in full National Association of Securities Dealers Automated Quotations U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on : CRUS), today announced the availability of a 64-bit GUI accelerator (CL-GD54UM36) for the unified memory architecture. This device offers OEMs greater price/performance flexibility for designing entry-to-mid level systems for the commercial PC market. Designed from the ground up to maximize graphics and system performance, this new accelerator utilizes a portion of the main system memory for the display, thus eliminating the chip count and cost of a separate frame buffer. Eliminating the separate frame buffer also reduces overall system power consumption while increasing reliability. "UMA (1) (Unlicensed Mobile Access) See GAN. (2) (Upper Memory Area) Memory in a PC between 640K and 1M. More relevant in the days of DOS, this region was broken into Upper Memory Blocks (UMB) reserved for video memory and other allows OEMs the flexibility to design systems with the exact combination of price and performance that users demand," said Douglas J. Bartek, president of Cirrus Logic's Visual & Systems Interface Company. "This flexibility can expand the entry-to-mid range classes of product within the commercial market segment, meeting a greater spectrum of needs. In our case, we offer a chip that's based on the proven core of Cirrus Logic's CL-GD5436, a high-performance EDO Edo: see Tokyo, Japan. DRAM-based accelerator. By using this proven core, we also leverage available software, further providing customers with cost and time-to-market advantages." Along with providing cost savings of between $20 to $40 per computer in frame buffer costs, the new device delivers up to 96 percent of standard graphics (non-UMA) performance in systems using 16 megabytes of system memory and L2 cache. It overcomes performance penalties associated with the CPU CPU in full central processing unit Principal component of a digital computer, composed of a control unit, an instruction-decoding unit, and an arithmetic-logic unit. and graphics subsystem sharing main memory by incorporating features that maximize system bandwidth utilization. These features address the two main causes of system performance degradation in UMA-based systems: reduced memory bandwidth for the CPU due to sharing main memory with the graphics subsystem, and reduced main memory size for the operating system due to a portion being used for display memory. To deliver maximum performance, the chip features asynchronous Refers to events that are not synchronized, or coordinated, in time. The following are considered asynchronous operations. The interval between transmitting A and B is not the same as between B and C. The ability to initiate a transmission at either end. memory clock operation at rates higher than the standard synchronous 66 MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. core logic host clock, and a larger CRT (1) (C RunTime) See runtime library. (2) (Cathode Ray Tube) A vacuum tube used as a display screen in a computer monitor or TV. The viewing end of the tube is coated with phosphors, which emit light when struck by electrons. FIFO (First In First Out) A storage method that retrieves the item stored for the longest time. Contrast with LIFO. See traffic engineering methods. FIFO - first-in first-out with intelligent management functions for effective memory bus arbitration. Optimized software drivers and a 64-bit wide interface (independent of display memory size) also contribute to improving memory bandwidth utilization and overall system performance. Features that boost main memory availability to the operating system include a flexible memory size and the associated software to control it. Display memory sizes of 512KB, 1MB and 2MB are supported, for resolutions of up to 1024 x 768 with 64K color and 800 x 600 with 8M color. The new chip allows users to select a display memory size that will accommodate the desired combination of display properties and performance level. "The memory industry's current transition to 16Mbit DRAMs is a major plus for UMA-based systems," said Mike Buchanan, director, PC Graphics for Cirrus Logic. "This trend, coupled with lower memory prices, is likely to drive a transition to a baseline of 16 megabytes of main system memory by the second half of this year. With 16 megabytes of memory and a UMA graphics device like the CL-GD54UM36, performance issues with the UMA environment will be negligible." The CL-GD54UM36 is compliant with VESA's UMA (VUMA VUMA VESA Unified Memory Architecture ) and Intel Corporation's Shared Memory Buffer Architecture (SMBA SMBA Stedelijk Museum Bureau Amsterdam SMBA Shared Memory Buffer Architecture SMBA San Marcos Baptist Academy (San Marcos, TX) SMBA Scottish Marine Biological Association SMBA Saskatoon Minor Basketball Association ) specifications. Since sampling of the part began, Cirrus Logic has been working with a number of core logic vendors, system BIOS suppliers, and PC motherboard OEMs. Prem Talreja, Opti's director of strategic marketing, noted that, "Opti's recently announced ViperMAX PCI (1) (Payment Card Industry) See PCI DSS. (2) (Peripheral Component Interconnect) The most widely used I/O bus (peripheral bus). chipset will support Cirrus Logic's CL-GD54UM36 graphics accelerator for all desktop UMA designs. Together, we expect Opti and Cirrus Logic to deliver superior solutions that address a broad range of price and performance options." Packaging, Pricing, and Availability The CL-GD54UM36 is a low-power CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. device packaged in a 208-pin plastic quad flat pack (PQFP (Plastic Quad Flat Package) Refers to many varieties of QFP chip packages, which are molded in plastic. See QFP. ). Sample quantities of the new device are available at $20 in quantities of 1,000. Volume production is planned for Q2 1996. Headquartered in Fremont, Calif., Cirrus Logic Inc. is a leading manufacturer of advanced integrated circuits for the desktop and portable computing, telecommunications, and consumer electronics markets. The Company applies its system-level expertise in analog and digital design to innovate highly integrated, software-rich solutions. Cirrus Logic has developed a broad portfolio of products and technologies for applications spanning multimedia, graphics, communications, system logic, mass storage, and data acquisition. -0- Note to Editors: Additional information about Cirrus Logic and its subsidiaries may be accessed on the World Wide Web at http://www.cirrus.com/ or via fax-on-demand at 800/359-6414 (dial 510/249-420 from outside the United States). CONTACT: Cirrus Logic Inc., Fremont Connie Duncan, 510/226-2346 (Editor contact) Tom Ramsey, 510/226-2386 (Reader contact) or Tsantes & Associates Nancy Sheffield, 408/452-8700 |
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