Circuit Semantics Meets 2003 Milestones, Unveils 2004 Plans.Business Editors/High-Tech Writers MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Jan. 15, 2004 Products Will Improve Performance and Simulator Support, Add Signal Integrity, Power Characterization, Noise and Functional Modeling Capabilities Circuit Semantics, Inc. (CSI CSI Crime Scene Investigator CSI CompuServe, Inc. CSI Commodity Systems, Inc. CSI Commodity Systems Inc. (Boca Raton, FL) CSI Crime Scene Investigation (CBS TV show) CSI Christian Schools International ), the leading provider of timing and characterization solutions for high-performance circuit design, today announced that it has achieved several significant milestones in the past year, and put together its 2004 product plan. Last year, the company licensed its patents for $9 million, closed a $1.6 million funding round with previous investors VenGlobal and Crescent Ventures leading the round and moved its headquarters to Mountain View, California For the census-designated place, see Mountain View, Contra Costa County, California. For other places called "Mountain View", see . Mountain View is a city in Santa Clara County, in the U.S. state of California. The city gets its name from the views of the Santa Cruz Mountains. . "The round of VC funding, licensing income, and growing interest from current and new customers are the elements that are allowing us to expand our staff and add new capabilities to our products this year," remarked Ewald Detjens, president and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of Circuit Semantics. In 2004, Circuit Semantics plans to add R&D engineers, marketing, sales and application staff, as well as features to its characterization and modeling tools. Sanjay Rohatgi, vice president of applications at Circuit Semantics, also noted, "We plan to add several significant product capabilities this year." 2004 Product Plans DynaCore(TM), in addition to its timing sign-off capabilities, will add signal integrity, power characterization and functional modeling. Thus, a single run of DynaCore will be able to characterize and analyze the design in various inter-dependent domains. This concurrent characterization and analysis is warranted by nanometer technology for successful silicon. Support for industry standard simulators will also be significantly enhanced, so customers using DynaCell(TM) with these simulators could experience up to a 7 to 10x performance improvement. In addition to DynaCell shipping now with noise characterization, plans are in place to add support for Synopsys' SPDM SPDM Special Purpose Dextrous Manipulator SPDM Scalable Polynomial Delay Model SPDM Single-Particle Density Matrix SPDM Sociedade Portuguesa de Doenças Metabólicas SPDM Sales Promotion Direct Mail format and the IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. 1603 Advanced Library Format (ALF ALF - Algebraic Logic Functional language ). More About Circuit Semantics Products Circuit Semantics offers DynaCell for characterization of cell libraries, DynaCore for timing sign-off and DynaModel(TM) for Verilog model generation of structured-custom designs. Models produced by the Circuit Semantics tools are used in synthesis, timing-driven place-and-route, static-timing analysis, noise analysis, power analysis and functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, . Tools are targeted for high performance ASICs, DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive , microprocessor and high-speed communications ICs. About Circuit Semantics Circuit Semantics, Inc. provides electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) software that supports precise, gate-level abstraction and analysis of transistor-level circuits, and accelerates timing closure for designs fabricated fab·ri·cate tr.v. fab·ri·cat·ed, fab·ri·cat·ing, fab·ri·cates 1. To make; create. 2. To construct by combining or assembling diverse, typically standardized parts: in nanometer process technologies. Circuit Semantics is headquartered at 2410 Charleston Road, Mountain View, CA 94043, telephone 650-564-9100; fax 650-564-9694. For more information, visit www.circuitsemantics.com.
Acronyms and definitions
ALF The Advanced Library Format or IEEE 1603 standard
is a standard for the language and semantic
representation for design libraries. It supports an
RTL to GDSII descriptions of functional, electrical
performance and layout views for technology libraries,
scalable from cells to complex hierarchical design
blocks.
IEEE Institute of Electrical and Electronic Engineers
SPDM The Scalable Polynomial Delay Model is a Synopsys
delay model used in the Liberty library.
DynaCell, DynaCore and DynaModel are trademarks of Circuit Semantics, Inc. All other trademarks are the property of their respective owners. |
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