Circuit Semantics Introduces a Fully Automated Solution for Noise Characterization; New Tool Enables Fast Generation of Liberty Noise Libraries.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--March 17, 2003

Circuit Semantics, Inc. (CSI), the leading provider of next generation modeling and characterization solutions for high-performance integrated circuit (IC) design, today announced DynaCell-SI, a fully automated characterization and modeling solution for signal integrity verification of cell-based digital ICs, including ASIC and customer-owned-tooling (COT) flows. DynaCell-SI provides the critical information required by signal integrity analysis tools to verify the level of tolerance of a design to the effects of noise and the impact on performance. This type of analysis is required to determine the reliability and manufacturability for circuits targeted for nanometer process technologies at 130 nm and below.

DynaCell-SI is based on the silicon proven and patented technology that Circuit Semantics uses in its characterization and modeling solutions for function, timing, and power. It creates a noise model that is completely consistent with the other views and includes the information required by the new signal integrity analysis solutions for evaluating noise calculation, noise immunity, and noise propagation.

"Today, more and more design teams designing high performance ASICs and using COT flows are using nanometer process technologies, which require very accurate cell models for timing and noise analysis for designs running beyond 300 MHz," said Ewald Detjens, chief executive officer at CSI. "Built on our market leading technology, DynaCell-SI provides the unique combination of speed, accuracy, and completeness required to determine the effects of the transistor behavior, as a result of noise, on the functionality of the design and its performance. This capability enables designers to find and correct critical problems prior to manufacture rather than waiting for silicon to discover any failures due to noise effects."

Importance of Accurate and Reliable Noise Characterization

"Nanometer effects and the impact of noise on the behavior of high-performance designs using nanometer processes can no longer be ignored," said Haroon Chaudhri, Circuit Semantics' VP of R&D. "Because of this situation, Circuit Semantics is taking its patented transistor-level characterization and modeling technology and using it to fill the gap for accurate noise characterization information required for reliable signal integrity analysis of cell-based digital designs."

According to research report by IBS (January 2002), for nanometer technology at 130 nm and below the impact of noise on signal integrity results in up to 50% increased probability of chip failure due to operating performance or functional problems. Failures may lead to costly silicon re-spins.

"Because of this impact, accurate and reliable noise characterization is a must for valid signal integrity analysis, which is used to determine the potential impact on the operation of the design by noise effects," continued Chaudhri.

Signal integrity analysis identifies signal distortions that affect timing and functionality, such as the ones due to cross talk, IR drop, and glitches. It evaluates the impact of noise propagation through circuit or "critical portions" of the circuits, and determines what structures are most susceptible to failure due to noise, as well as the effects of noise on delays and slew.

DynaCell-SI Features

DynaCell-SI provides automatic transistor level characterization of cells for noise with minimal designer intervention. For the characterization of the cells, DynaCell-SI automatically identifies the functionality of the cell. It generates a comprehensive and non-redundant vector stimuli for characterization, characterizes the cell for noise using SPICE simulation, and generates a library model based on Synopsys' open Liberty(TM) library standard. The product only requires as input the SPICE netlist and process model for each cell, and user information on desired ranges for glitch heights and widths, voltages, and output loads. Unlike conventional tools that require templates and scripts, DynaCell-SI uses an algorithmic and patented approach to determine the cell functionality and generate the input vectors. After the library models are created, the designer can use them for signal integrity sign-off using PrimeTime(R) SI in Synopsys' Galaxy Design Platform.

Noise measurements in the generated models include: cell output steady state, I/V characteristics, cell noise immunity and DC noise margins, propagated noise through the cell. For I/V characteristics, the designer can provide voltage sweep ranges and steps. For noise immunity and propagation, the designer can provide glitch width, glitch height, output load, and cell failure criterion.

In addition, DynaCell-SI is integrated seamlessly with the rest of Circuit Semantics' characterization and modeling product offering, which enables the creation of a single model in a single run that includes the consistent and complete function, timing, power, and noise information required for verification to achieve design closure and reliable manufacturability of high-performance designs using nanometer process technologies at 130 nm and below. The accuracy and quality of results will help save silicon re-spins, which translates into a direct savings of up to several million dollars just in mask and fabrication costs.

Pricing and Availability

DynaCell-SI is available directly from Circuit Semantics, Inc. Please contact Circuit Semantics for pricing information on time-based and perpetual licenses. DynaCell-SI is supported on Sun Solaris, HP-UX, and Linux platforms.

About Circuit Semantics, Inc.

Circuit Semantics, Inc. provides timing and characterization solutions for high performance cells, cores, and blocks based on innovative and patented technology. IC designers employ these mixed-level solutions to create high-performance chips using full-custom and structured-custom methodologies. The company's products support precise, gate-level abstraction of transistor-level circuits to accelerate timing closure for designs fabricated in deep submicron (DSM) process technologies. These solutions are especially well suited for the microprocessor, digital signal processing, graphics, and high-speed communications markets. Circuit Semantics is headquartered at 2590 North First Street, Suite 301, San Jose, California 95131, telephone [phone]; fax [phone]. For more information, visit www.circuitsemantics.com.

Note to Editors: Circuit Semantics and DynaCell are registered trademarks of Circuit Semantics, Inc. PrimeTime and Synopsys are registered trademarks of Synopsys, Inc. Galaxy and Liberty are trademarks of Synopsys, Inc.