Chrysalis to Develop Formal Verification for New ARM7TMDI-S Core.NORTH BILLERICA, Mass.--(BUSINESS WIRE)--June 22, 1998--Chrysalis today announced that they will develop a formal verification
In the context of hardware and software systems, formal verification flow for ARM's new synthesized version of the ARM7TDMI core, the ARM7TDMI-S core using their Design VERIFYer. "We are very excited to be working with one of the leading IP suppliers in the market," states Isadore Katz, President of Chrysalis chrysalis (krĭs`əlĭs): see pupa. Symbolic Design. "Our customers have told us that formal verification is essential to their Systems on a Chip design flows. This relationship will be critical to our delivering a complete formal solution to the engineer." One of the key challenges facing System-on-Chip (SoC) design teams is how to verify their chips when using third party IP. ARM has put together an extensive set of verification checks to help the engineer put ARM's cores into system designs. Synthesized IP cores pose a special challenge. After RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; verification, to make sure that the core functions correctly with the rest of the chip, it is necessary to check that no changes to the core's functionality were inadvertently introduced by any of the subsequent implementation steps such as synthesis, test or layout. Equivalence checking is the methodology of choice for many users today for gate level functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, . Using equivalence checking, users are able to prove that the gate level netlists or layout netlists correctly implement the original RTL. In the case of a third party IP core such as the ARM7TDMI-S, the user can prove the gate level implementation of the core matches the RTL. "Our goal is to deliver our synthesizable ARM core to designers so that it matches their existing design and verification methodologies," said Tim Hopes, Electronic Design Automation, engineering manager for ARM. "Working closely with Chrysalis will give our customers the verification tool they will need to design in ARM's synthesizable core quickly and effectively." This is a continuation of our general strategy to support ARM and their customers' SoC design flow methodologies. Chrysalis Design VERIFYer is one of the main products, in production today, that address customers needs for formal verification as part of the overall SoC development. CHRYSALIS SYMBOLIC DESIGN Chrysalis Symbolic Design, Inc. headquartered in Massachusetts, is the premier supplier of software products that use formal methods to automate the design of advanced digital integrated circuits Integrated circuits Miniature electronic circuits produced within and upon a single semiconductor crystal, usually silicon. Integrated circuits range in complexity from simple logic circuits and amplifiers, about 1/20 in. (1. . These products provide complete, independent verification of the logic design and implementation process to improve engineering productivity and reduce Time-to-market. An enabling technology, formal methods are a critical part of the design strategy for complex, high-speed deep submicron ASICs and ICs. Formal design and verification tools from Chrysalis include Design VERIFYer(R) formal equivalence checking Formal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated circuits, to formally prove that two representations of a circuit design exhibit exactly the same behavior. software, Design EXPLORE; interactive formal debugging (programming) debugging - The process of attempting to determine the cause of the symptoms of malfunctions in a program or other system. These symptoms may be detected during testing or use by real users. software, and the new Design INSIGHT(R) formal model checking products. The company has sales and support personnel in all three major world markets -- the US, Europe and Asia. WEB site access is through http://www.chrysalis.com. ARM, Thumb, StrongARM and ARM Powered are registered trademarks of ARM Limited. ARM7TDMI and ARM7TDMI-S are trademarks of ARM Limited. All other brands or product names are the property of their respective holders. "ARM" is used to represent ARM Holding plc (LSE LSE - Language Sensitive Editor :ARM) and (NASDAQ NASDAQ in full National Association of Securities Dealers Automated Quotations U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on :ARMHY); it's operating company operating company A business that engages in transactions with outsiders. ARM Limited; and the regional subsidiaries ARM INC; ARM KK; ARM Korea Ltd.
CONTACT: Chrysalis Symbolic Design, Inc.
Karen Wills, 978/436-9909
or
MRTech
Frank Rich, 860/779-3220
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