ChipX and Northwest Logic Announce a Complete 667Mbps DDR/DDR2 SDRAM Structured ASIC Solution.SANTA CLARA Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif. -- ChipX Inc., Structured ASIC Leader, and Northwest Logic offer a complete DDR/DDR2 SDRAM (Synchronous DRAM) A type of dynamic RAM (DRAM) memory chip that has been widely used since the late 1990s. SDRAM chips eliminated wait states by dividing the chip into two cell blocks and interleaving data between them. solution with speeds up to 667Mbps, including a DDR/DDR2 PHY See physical layer and physical. and DDR/DDR2 SDRAM Controller Cores for use on all CX6000 Structured ASIC products. All DDR/DDR2 SDRAM chip designs require close integration of the physical interface (PHY) with both the chip process and the memory controller core in order to meet tight memory timing requirements. Third-party PHY designs often require extensive custom engineering to meet performance specifications of a specific process, and often do not integrate well with the target memory controller core, leading to a significant challenge for the chip designer. The ChipX solution solves this design challenge by offering a DDR/DDR2 PHY design built entirely out of logic cells (X-Cells[TM]) on the CX6000 130nm family of Structured ASIC products. This PHY has been integrated and verified with the configurable memory controller cores from Northwest Logic. The ChipX DDR/DDR2 PHY can be placed next to any CX6000 I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output bank and supports any bus width in 8 bit increments. Because the PHY design is implemented as an overlay and does not reside in the basic gates, there is no penalty if it is not placed. The Northwest Logic DDR (Double Data Rate) Refers to an SDRAM memory chip that increases performance by doubling the effective data rate of the frontside bus. For more details, see SDRAM. DDR - Double Data Rate Random Access Memory and DDR2 Memory Controller Cores provide extremely high bus efficiency using Request Reordering re·or·der v. re·or·dered, re·or·der·ing, re·or·ders v.tr. 1. To order (the same goods) again. 2. To straighten out or put in order again. 3. To rearrange. v. , Bank Management and Look-Ahead processing. The cores can also be configured during design or real-time to work with any memory configuration. Northwest Logic also provides separate ECC (1) (Error-Correcting Code) A type of memory that corrects errors on the fly. See ECC memory. (2) (Elliptic Curve Cryptography) A public key cryptography method that provides fast decryption and digital signature processing. , Read-Modify-Write, and Multi-Port Front-End add-on modules to enable each design to be optimally configured. The cores support the very high memory clock rates and have a minimal gate count. "The ChipX DDR/DDR2 PHY solution is unique, because customers get the maximum performance without any integration effort, yet don't pay any penalty for the flexibility this design offers," said Wouter Suverkropp, Director of Marketing at ChipX. "If a DDR/DDR2 SDRAM solution is required, the DDR/DDR2 PHY and memory controller core are placed in the CX6000 fabric as a firm macro with guaranteed performance. If you don't need such a solution, you just use the gates for something else, without any overhead." "The integration of the ChipX DDR/DDR2 PHY with the Northwest Logic DDR and DDR2 memory controllers provides a high-performance, easy-to-use SDRAM solution," said Brian Daellenbach, President of Northwest Logic. "Customers can use this solution to quickly develop and bring to market chips that incorporate a DDR/DDR2 SDRAM interface". The ChipX DDR/DDR2 PHY is shipping in customer silicon today, and is available as a macro on any CX6000 130nm Structured ASIC, including an extensive range of products with USB USB in full Universal Serial Bus Type of serial bus that allows peripheral devices (disks, modems, printers, digitizers, data gloves, etc.) to be easily connected to a computer. 2.0 HS OTG (1) See USB OTG. (2) (The OBJECTive Technology Group, Ltd., Alexandria, VA) An organization that was devoted to distributed computing and object technology. Founded in 1994, it augmented the object and Internet standards community and served as an intermediary between and PCI Express. For more information, contact www.chipx.com or call +1 408 988 2445 Northwest Logic's DDR/DDR2 SDRAM Controllers are shipping in silicon today and are fully available. For more information, contact www.nwlogic.com or call 503-533-5800 x309. About ChipX ChipX, Inc. is a pioneer and leading manufacturer of late-stage programmable application-specific integrated circuits, or Structured ASICs. The company's innovative, patented technology consolidates wafer production tooling, reduces time-to-market and minimizes the total cost to profit. ChipX Structured ASIC technology is widely used in consumer equipment, computing peripherals, communication systems, industrial control, medical equipment, instrumentation and military/aerospace systems. For more information about ChipX families of Structured ASICs, please visit www.chipx.com. Headquartered in Santa Clara, CA, ChipX is a privately held corporation Noun 1. privately held corporation - a corporation owned by a few people; shares have no public market close corporation, closed corporation, private corporation , founded in the U.S. in 1989. A subsidiary, ChipX (Israel) Ltd., performs Research & Development. Investors include Elron Electronic Industries, Ltd. (NASDQ:ELRN), VantagePoint Venture Partners, Wasserstein Venture Capital, Newlight Associates, Parker Price Venture Capital, UMC UMC United Methodist Church UMC United Microelectronics Corporation UMC University Medical Center UMC United Microelectronics Corp (Republic of China) UMC University of Missouri-Columbia , Needham Capital Partners and Insite Capital. About Northwest Logic Northwest Logic, founded in 1995 and located in Beaverton, Oregon, provides high-performance, easy-to-use IP cores for FPGAs and ASICs. These IP cores include memory controller, PCI Express and PCI (1) (Payment Card Industry) See PCI DSS. (2) (Peripheral Component Interconnect) The most widely used I/O bus (peripheral bus). cores. Key benefits of Northwest Logic's IP cores include: Co High performance -- support high clock rate and high throughput Co Easy to use -- simple user interface, easy to configure, etc. Co Fully hardware validated Co Provided with a comprehensive verification suite Co Support for Chipx Structured ASIC platform and FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. prototyping Co Development boards and driver support available Co Top quality technical support Co Customization and integration services available For additional information, visit www.nwlogic.com [c] 2006 ChipX Inc. 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