Chip Express Integrates High Performance DSP Capability into Structured ASIC Products.

Business Editors/High-Tech Writers

SANTA CLARA, Calif.--(BUSINESS WIRE)--Feb. 3, 2004

Chip Express, the Structured ASIC leader, today announced the availability of high performance DSP capability for its entire Structured ASIC product line.

By creating core logic optimized to take advantage of Synopsys' popular DesignWare(R) Library datapath generators, Chip Express is enabling designers to achieve near cell-based ASIC performance from Chip Express' Structured ASIC technology. Designers using Chip Express Structured ASICs can automatically realize significant gains in performance and logic efficiency by having their register transfer level (RTL) DSP designs compiled using Synopsys' Design Compiler(R) and DesignWare Library.

"Our Structured ASIC core logic was developed with performance in mind," said Steve Bateman, vice president of Engineering at Chip Express. "Each logic element can be configured into a variety of primitive cells suitable for synthesis. We've optimized our combinational cells to take advantage of Synopsys' DesignWare Library to generate high-performance and area-efficient adders, multipliers and other datapath and DSP components."

Chip Express' 0.18um CX5000 DSP performance now rivals 0.18um standard cell. Bateman indicated that a recent test showed a 32-bit multiplier using CX5000 taking just 3.6ns, compared to a widely used 0.18um standard cell's propagation delay of 3.0ns, and vastly better than the fastest 0.13um FPGA at over 11ns.

"A factor of three performance advantage over FPGA is an important innovation," added Bateman. "Closing timing in modern FPGAs can be a real chore, so we expect many designers to focus on Structured ASIC for production, using FPGA for algorithm verification only."

"DesignWare Library has been the technology of choice for DSP implementation in standard cell for many years," said Ed Bard, director of marketing for Synopsys' DesignWare Library. "Because of the work that Chip Express has done to optimize their core logic cells to take advantage of DesignWare Library, we expect that designers will see performance increases in their DSP and other arithmetically intensive designs targeting the Chip Express Structured ASIC product families."

Pricing and Availability

Designers with a current Synopsys DesignWare Library and Chip Express Structured ASIC licenses, have immediate access, for no additional charge, to the high-performance DSP capability. Chip Express can also provide RTL compilation services using Synopsys Design Compiler and DesignWare Library for RTL hand-off customers. More information including DSP performance benchmarks are available on the company's website at www.chipx.com/dsp. Additional information about Synopsys DesignWare Library and other available DesignWare IP is available at www.designware.com.

About Chip Express

Chip Express is a leading manufacturer of late-stage programmable application-specific integrated circuits, or Structured ASICs. The company's innovative, patented technology consolidates wafer production tooling, reduces time-to-market and minimizes the cost of initial production. Chip Express's Structured ASIC technology is widely used in automotive telematics, computing peripherals, communications, high-end consumer electronics, industrial control, medical equipment and military/aerospace systems. Headquartered in Santa Clara, Calif., Chip Express is a privately held corporation, founded in the U.S. in 1989. A subsidiary, Chip Express (Israel) Ltd., performs Research & Development.

Chip Express is a privately held company. First-round venture capital financing came from Elron Electronic Industries, Ltd. (Nasdaq:ELRN), a 34% shareholder in the company. Subsequent rounds involved Toyo Ink Mfg. Co., Ltd., Morgan Stanley Venture Partners, Agere Systems, Wasserstein Venture Capital, Newlight Associates, Parker Price Venture Capital, manufacturing partner UMC (NYSE:UMC), and Needham Capital Partners.

This press release contains forward-looking statements based on current information available to Chip Express Corporation as of the date hereof. These statements are based on Management's current expectations and may ultimately prove to be incorrect or false. Factors which could cause future results to differ materially from the results discussed, implied, or forecasted in the forward-looking statements include delays in scheduled product availability dates (which could result from various occurrences including development or testing difficulties, software errors, shortages in appropriately skilled engineers and project management problems); the risks inherent in the commercialization of the Company's anticipated products and services; shifts in customer or market demand for the Company's anticipated products; the impact of competitive products and pricing; and possible disruptive effects of organizational changes, including retaining key personnel and coordinating operations. Chip Express assumes no obligation to revise or update any forward-looking statements contained in this press release.

Synopsys, DesignWare, and Design Compiler are registered trademarks of Synopsys, Inc. All other products or service names mentioned herein are the property of their respective owners.