Chip Express, Lightspeed, Synplicity, and Tera Systems Team Up to Establish the ''Structured ASIC Association''; Alliance Launches Website to Promote Structured ASIC Technology.Business Editors/High-Tech Writers SANTA CLARA Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif.--(BUSINESS WIRE)--Feb. 11, 2004 A group of Structured ASIC A type of application specific IC (ASIC) chip that contains blocks of logic, called "tiles" or "modules," that have their transistors already wired together forming gates along with some combination of multiplexors, flip/flops, look up tables and the like. manufacturers and EDA companies  The external links in this article or section may require cleanup to comply with Wikipedia's content policies. -- Chip Express, Lightspeed, Synplicity, and Tera Systems -- today announced that they have formed the "Structured ASIC Association" (SAA (Systems Application Architecture) A set of interfaces designed to cross all IBM platforms from PC to mainframe. Introduced by IBM in 1987, SAA includes the Common User Access (CUA), the Common Programming Interface for Communications (CPI-C) and Common Communications ). The founding members are collaborating to firmly establish Structured ASICs as a unique market segment and educate the industry about this new technology. Launched today by the SAA, the new Structured ASIC website (www.structuredasic.com) was developed to provide a comprehensive source of information about Structured ASIC technology. The site provides direct access to the latest Structured ASIC news, gives detailed information about the technology, and explains the benefits associated with Structured ASICs. Fast Turnaround, Low Cost As defined by the SAA, Structured ASICs are a new category of semiconductors targeted at customers who are looking for Looking for In the context of general equities, this describing a buy interest in which a dealer is asked to offer stock, often involving a capital commitment. Antithesis of in touch with. the fast-turn capabilities of FPGAs without their high unit cost, and those who want to take advantage of the relatively low unit costs of ASICs without paying high NREs. Structured ASIC devices reduce much of the up-front NRE (Non-Recurring Engineering) Refers to the cost of creating a new product, which is paid up front. Contrast with "production cost," which is ongoing and based on the quantity of material produced. and shorten development time by using pre-diffused base metal layers to implement logic cells, memory and I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output common to many designs. Custom logic for a specific application is then implemented in the final few layers of metal, requiring far fewer mask layers for each design. Customers using Structured ASICs reap many of the performance and cost advantages of a full custom ASIC in a device which can be fabricated in as little as three weeks. Using this revolutionary new technology, design teams can build complex ASICs for 25 percent or less of the development cost of a standard cell device, at a unit cost approximately 90 percent less than a complex FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. . Both large OEMs and emerging technology firms are implementing Structured ASICs in a wide variety of market segments, including telecommunications, high-speed video processing, medical and other industrial applications. Recently released research by iSuppli shows the nominal forecast of Structured ASIC revenue reaching $250 million by the year 2007. Another study by In-Stat/MDR predicts significant growth in the Structured ASIC market over the next several years. "As a consequence of the cost and time-to-market divergence occurring between the FPGA and standard cell markets, the semiconductor industry is changing and the market demanded we produce statistics to support the obvious," commented Jerry Worchel, senior analyst with In-Stat/MDR. "Structured ASICs are here and they'll be here well into the future. To show the importance In-Stat/MDR attaches to this technology, we recently published a report on this market, showing nearly a 150% CAGR CAGR See: Compound Annual Growth Rate , between 2002 and 2007." About The Structured ASIC Association The Structured ASIC Association was formed to establish and promote the Structured ASIC market segment and name. The goals of the association are to establish Structured ASIC as a unique ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. segment within the analysts/media community, and to educate and inform the market of the benefits of Structured ASIC technology. The SAA defines a Structured ASIC as "an integrated circuit architecture that delivers reduced entry cost and faster time to silicon using a predefined arrangement of late-stage mask-customizable logic and pre-diffused macros." This means customers can expect low NRE, low unit pricing, and fast turnaround time (1) In batch processing, the time it takes to receive finished reports after submission of documents or files for processing. In an online environment, turnaround time is the same as response time. for prototype and production Structured ASIC devices. For more information, please visit the Structured ASIC website at www.structuredasic.com. The Structured ASIC Association is open to new members who actively participate in the Structured ASIC market. Interested parties can contact member representatives listed below for more information. About Chip Express Chip Express is a leading manufacturer of high performance Structured ASICs (Application Specific Integrated Circuits). The company's innovative, patented technology consolidates wafer manufacture tooling, reduces time-to-market and minimizes the cost of initial production. The company's Structured ASIC technology is widely used in high-end consumer electronics, communications, automotive telematics, computing peripherals, industrial control, medical equipment and military/aerospace systems. Headquartered in Santa Clara, CA, Chip Express is a privately held corporation Noun 1. privately held corporation - a corporation owned by a few people; shares have no public market close corporation, closed corporation, private corporation , founded in the U.S. in 1989. The company holds two subsidiaries: Chip Express (Israel) Ltd., which performs Research & Development, and Chip Express UK Ltd., which manages European operations. For more information, visit the Chip Express website at http://www.chipexpress.com. About Lightspeed Lightspeed Semiconductor is the premier supplier of structured array technology to the semiconductor industry. We invented the structured array to reduce semiconductor development expense by an order of magnitude A change in quantity or volume as measured by the decimal point. For example, from tens to hundreds is one order of magnitude. Tens to thousands is two orders of magnitude; tens to millions is three orders of magnitude, etc. , while accelerating time-to-market up to six months vs traditional design methods. Our structured array technology leads the industry in lower costs, higher density and performance, and fastest time-to-silicon. Lightspeed's customers include both fabless and IDM (1) See identity management. (2) (Integrated Device Manufacturer) A company that performs every step of the chip-making process, including design, manufacture, test and packaging. Examples of IDMs are Intel, AMD, Motorola, IBM, TI and Lucent. semiconductor manufacturers. For more information visit http://www.lightspeed.com. About Synplicity, Inc. Synplicity Inc. (Nasdaq:SYNP SYNP Synchronization Profile ) is a leading provider of software products that enable the rapid and effective design and verification of semiconductors used in networking and communications, computer and peripheral, consumer and military/aerospace electronics systems. Synplicity leverages its innovative logic synthesis, physical synthesis and verification software solutions to improve performance and shorten development time for complex programmable logic devices, application specific integrated circuits (ASICs), Structured ASICs and system-on-chip (SoC) integrated circuits. The company's fast, easy-to-use products offer high quality of results, support industry-standard design languages (VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. and Verilog) and run on popular platforms. Synplicity employs over 260 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, Calif. For more information on Synplicity, visit http://www.synplicity.com. About Tera Systems, Inc. Tera Systems, Inc. provides a leading front-end design planning solution for integrated circuits that results in first-time silicon success in record time. Tera's patented RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; design-planning product is the only solution that lets front-end designers build accurate, predictive models to identify root causes of potential problems rather than symptoms, fix these before they occur, hand-off designs at the RTL level for back-end implementation, and produce chips that perform as expected. Endorsed by top semiconductor companies, Tera also provides specialized optimization for Structured ASIC designs, further reducing turnaround time and costs for these applications. It gives front-end designers needed visibility into the timing and physical restrictions imposed by Structured ASIC architecture. For more information, visit the Tera Systems web site at http://www.terasystems.com. |
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