Celoxica Extends the Software-Compiled System Design Advantage.Business Editors/High-Tech Writers ABINGDON, England--(BUSINESS WIRE)--Feb. 16, 2004 Release 3.0 of DK Design Suite adds re-timing synthesis and new co-simulation manager to leading FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. system design environment Celoxica Limited today announced the release of the DK Design Suite, version 3.0, extending the functionality of their high-productivity design environment for system FPGA devices. The latest suite includes the DK3 system design tool for synthesis of complex C-based algorithms directly to FPGA, Nexus-PDK3 for co-verification of hardware with software models and the PDK PDK Phi Delta Kappa (professional organization for teachers) PDK Portal Development Kit (SAP Enterprise Portal) PDK Peachtree-Dekalb Airport (Atlanta, GA, USA) 3 processor and board support packages for rapid system prototyping to hands-on hardware. The new features in DK3 provide improved quality of results for the hardware implemented from C-based models. The Handel-C synthesis tool now performs re-timing of hardware critical paths, automatic use of FPGA combinatorial multipliers and on-chip resources, and automatic pipelining of synchronous memory blocks. The new synthesis features give users the ability to perform speed/area tradeoffs directly from their C algorithms, realizing significant performance improvements of 100% or more without requiring changes to their source code. The Celoxica DK3 software continues to support all the latest FPGA devices from Altera and Xilinx and a number of other established and emerging reconfigurable architectures. The latest features in version 3.0 of Nexus-PDK, Celoxica's co-simulation environment, include a new co-simulation manager that handles multiple simulation environments concurrently, manages data linking and global clocks across simulations, and eases user setup of the system co-verification environment. The Nexus-PDK environment supports co-simulation of cycle accurate C, C++ and Handel-C models with SystemC, MATLAB/Simulink, and VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. and Verilog simulators Verilog simulation software has come a long way since its early origin as a single proprietary product offered by one company. Today, Verilog simulators are available from many vendors, at all price points. . The PDK3 processor support packages provide improved performance for processor cores commonly used in Altera and Xilinx FPGAs. The PDK3 Data Streaming Manager (DSM 1. DSM - Data Structure Manager. An object-oriented language by J.E. Rumbaugh and M.E. Loomis of GE, similar to C++. It is used in implementation of CAD/CAE software. DSM is written in DSM and C and produces C as output. ) API and simulation software Simulation software is based on the process of imitating a real phenomenon with a set of mathematical formulas. It is, essentially, a program that allows the user to observe an operation through simulation without actually running the program. supports ARM and NIOS NIOS - Netware Input/Output Subsystem processors in Altera devices and Microblaze and PowerPC processors General-purpose PowerPC processors IBM/Motorola
2. PSL - Problem Statement Language. See PSL/PSA. ) and Platform Application Layer (PAL) API libraries to speed up system prototyping and board reuse across projects. The market acceptance of the Celoxica DK Design Suite was excellent in 2003. Celoxica maintained a 70% growth rate year over year and sold the 300th commercial DK license in 2003. "The new features in the DK3 release will only support that trend by making the design environment even more productive for implementing complex C algorithms in FPGA," said Jeff Jussel, vice president of marketing at Celoxica. Pricing and Availability The DK Design Suite Version 3.0 will be available for general delivery in March 2004. Version 3.0 will be available across all Celoxica product configurations with prices starting at U.S. $2000 for the Platform Developer's Package configuration. The software supports computing platforms with Windows 2000 and Windows XP. Celoxica also offers a broad range of signal processing IP, design services and off-the-shelf FPGA prototyping cards to support the DK Design Suite and the Software-Compiled System Design methodology. About Celoxica An innovator in system-level electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ), Celoxica supplies the design technology, IP and services that define Software-Compiled System Design, a methodology that exploits higher levels of design abstraction to dramatically improve silicon design productivity. Celoxica's products address hardware/software partitioning, co-verification and C-based synthesis to reconfigurable hardware. Established in 1996, Celoxica offers a proven route from complex software algorithms to hardware, and provides an ideal design environment for System FPGA with significant productivity advantages for digital signal processing See DSP. Digital Signal Processing - (DSP) Computer manipulation of analog signals (commonly sound or image) which have been converted to digital form (sampled). applications such as imaging, electronic security and communications. For more information, visit: www.celoxica.com. Note to Editors: Celoxica, Handel-C and the Celoxica logo are trademarks of Celoxica, Ltd. All other brand names and product names are the property of their respective owners. |
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