Celoxica Delivers ESL Implementation Path for Altera's HardCopy II Structured ASICs; Celoxica Introduces C-based ESL Design and Synthesis Flow To Dramatically Reduce Multi-Million Gate Simulation and Verification Times.ABINGDON, England -- Celoxica Ltd., the leading provider of C-based electronic system level (ESL (1) An earlier family of client/server development tools for Windows and OS/2 from Ardent Software (formerly VMARK). It was originally developed by Easel Corporation, which was acquired by VMARK. ) design and synthesis solutions, today announced support for Altera's HardCopy II structured ASIC A type of application specific IC (ASIC) chip that contains blocks of logic, called "tiles" or "modules," that have their transistors already wired together forming gates along with some combination of multiplexors, flip/flops, look up tables and the like. family in Agility Compiler for SystemC and the DK Design Suite. The tools and methodology support a seamless flow from algorithm and transaction level model (TLM TLM Telemetry TLM Transaction Level Modeling TLM Tout Le Monde (French) TLM The Leprosy Mission (Northern Ireland) TLM Transmission Line Matrix TLM The Little Mermaid (fairy tale) ) to Stratix II FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. prototype, and then to HardCopy II structured ASIC. The ESL design flow and FPGA front-end speeds verification and design productivity and enables algorithm acceleration in Structured ASIC by providing a direct path for silicon implementation from SystemC models and ANSI-C software. "There is an increasing emphasis in the volume digital-image and signal-processing markets to accelerate algorithms in flexible, low-power, high-performance silicon, with more of the design and verification effort being moved to the system level to tackle the inherent complexity," said Jeff Jussel vice president of marketing for Celoxica. "Couple this with relentless pressures on time-to-market, cost and designer productivity, our C-based design and synthesis technology provides the most cost-effective design and implementation route from Algorithm and TLM to HardCopy II structured ASIC." Targeted at the growing number of designers who have less time to develop and differentiate high-performance complex designs, Celoxica's ESL tools dramatically reduce multi-million gate simulation and verification times compared to traditional design flows and speed implementation by automatically generating RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; descriptions and EDIF EDIF - Electronic Design Interchange Format. Not a programming language, but a format to simplify data transfer between CAD/CAE systems. LISP-like syntax. See also Berkeley EDIF200. E-mail: <edif-support@cs.man.ac.uk> ftp://edif.cs.man.ac.uk/pub/edif. netlists from SystemC and Handel-C. Designers using Altera's HardCopy II can exploit the array of hardware logic optimizations Logic optimization a part of logic synthesis, is the process of finding an equivalent representation of the specificied logic circuit under one or more specified constraint. Generally the circuit is constrained to minimum chip area meeting a prespecified delay. available in the Agility Compiler and DK Design Suite to quickly develop high-performance, area-efficient implementations. "HardCopy II structured ASIC provides the only seamless prototype to structured ASIC production migration in the market," said Alain Bismuth bismuth (bĭz`məth) [Ger. Weisse Masse=white mass], metallic chemical element; symbol Bi; at. no. 83; at. wt. 208.9804; m.p. 271.3°C;; b.p. about 1,560°C;; sp. gr. 9.75 at 20°C;; valence +3 or +5. , VP HardCopy Business Group, Altera Corporation. "Supported by Celoxica's Agility Compiler for SystemC and DK Design Suite, designers can leverage the benefits of C-based ESL design with HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. and block-based approaches. This integration provides a common development platform for system, algorithm and hardware designers when targeting the HardCopy II structured ASIC." About Celoxica An innovator in Electronic System Level (ESL) design, Celoxica is turning software into silicon by supplying the design tools, boards, IP and services that enable the next generation of advanced electronic product design. Celoxica technology raises design abstraction to the algorithm level, accelerating productivity and lowering risk and costs by generating semiconductor hardware directly from C-based software descriptions. Adding to a growing installed base, Celoxica provides the world's most widely used C-based behavioral design and synthesis solutions to companies developing semiconductor products in markets such as consumer electronics, defense and aerospace, automotive, industrial and security. For more information, visit: www.celoxica.com. Celoxica and the Celoxica logo are trademarks of Celoxica, Ltd. All other brand names and product names are the property of their respective owners. |
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