Calypto to Present at Silicon Valley EDA Tech Forum.Presentation Outlines System Level Methodology for RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; Verification SANTA CLARA Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif. -- Calypto[TM] Design Systems, Inc., the leader in sequential analysis In statistics, sequential analysis is statistical analysis where the sample size is not fixed in advance. Instead data is evaluated as it is collected, and further sampling is stopped in accordance with a pre-defined stopping rule as soon as significant results are observed. technology, will present, "An Automated Methodology for Verifying System-Level Algorithms versus RTL Code Using Sequential Equivalency Checking," during the EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. Tech Forum Monday, October 9, at the Santa Clara Convention Center in Santa Clara, Calif. Calypto will be available during the vendor fair to discuss a system-level methodology and demonstrate SLEC SLEC Software de Libre Redistribución y Educación en Colombia SLEC South Louisiana Economic Council SLEC Slavica Ecclestone Corporation SLEC Satellite Local Exchange Carrier SLEC Sheep Lice Eradication Campaign SLEC Summary List of Equipage Changes [TM], its Sequential Logic Equivalence Checker for system to register transfer level (RTL) verification. The presentation, part of the electronic system level (ESL (1) An earlier family of client/server development tools for Windows and OS/2 from Ardent Software (formerly VMARK). It was originally developed by Easel Corporation, which was acquired by VMARK. ) session, runs from 2-2:50 p.m. It will introduce a structured, reusable system-level methodology for effective RTL verification and introduce the SLEC product family, a key part of a comprehensive methodology for bridging system and RTL design. For more details on Calypto and its SLEC product family, visit: http://www.calypto.com. For the complete agenda and registration information for the EDA Tech Forum, go to: http://www.edatechforum.com/events/santa_clara/index.cfm About Calypto Founded in 2002, Calypto Design Systems, Inc. enables SoC design teams to bridge System and RTL for semiconductor design, saving millions of dollars in design costs and silicon re-spins. It delivers software products to leading edge semiconductor and systems companies worldwide. Calypto is privately held with venture funding from Cipio Partners, JAFCO Ventures, Tallwood Venture Capital and Walden International. It is a member of the Cadence Connections program, the IEEE-SA IEEE-SA Institute of Electrical and Electronic Engineers-Standard Association , Synopsys SystemVerilog Catalyst Program, and the Mentor Graphics OpenDoor program. Corporate Headquarters are located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: (408) 850-2300. Email: info@calypto.com. More information about Calypto may be found at: http://www.calypto.com. Calypto and SLEC are trademarks of Calypto Design Systems Inc.. Other products and company names may be trademarks or registered trademarks of their respective companies. |
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