Cadence launches single-kernel verification platform. (Hot wires: news just off the press).

SAN JOSE -- Cadence Design Systems has launched what it claims is the first single-kernel verification platform for nanometer-scale designs that supports a unified methodology for embedded software, control, data path, and analog/mixed-signal/RF design domains. Called Incisive, the new platform's unified methodology reportedly cuts testbench development time, verification runtime and debug time, and can compress overall verification time by as much as half, Cadence says.

The platform provides native support for Cadence's Verilog, VHDL, SystemC, the SystemC Verification Library, property specification language PSL/Sugar, algorithm development and Analog/Mixed Signal. It also supports existing verification approaches.

Cadence rolled out three tools with the platform: Incisive, for simulation-based, digital verification; Incisive-XLD, for collaboration up to 10 seats; and Incisive-XLD Base, which combines Incisive-XLD with a Palladium accelerator/emulator.

Incisive-XLD has a special "acceleration" that extends to a million gates of acceleration capacity, reportedly delivering 100 to 10,000 times the performance of simulation. Cadence says this option permits design and verification teams to work simultaneously, then runs up to a billion verification cycles overnight.