Cadence launches single-kernel verification platform. (Hot wires: news just off the press).SAN JOSE San Jose, city, United States
San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. -- Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services.
See also Verilog. has launched what it claims is the first single-kernel verification platform for nanometer-scale designs that supports a unified methodology for embedded software Instructions that permanently reside in a ROM or flash memory chip. Embedded software may be immediately available to the CPU or, for faster execution, may be transferred to RAM first and then executed. , control, data path, and analog/mixed-signal/RF design domains. Called Incisive, the new platform's unified methodology reportedly cuts testbench development time, verification runtime and debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. time, and can compress overall verification time by as much as half, Cadence says.
The platform provides native support for Cadence's Verilog, VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. , SystemC, the SystemC Verification Library, property specification language PSL/Sugar, algorithm development and Analog/Mixed Signal. It also supports existing verification approaches.
Cadence rolled out three tools with the platform: Incisive, for simulation-based, digital verification; Incisive-XLD, for collaboration up to 10 seats; and Incisive-XLD Base, which combines Incisive-XLD with a Palladium accelerator/emulator.
Incisive-XLD has a special "acceleration" that extends to a million gates of acceleration capacity, reportedly delivering 100 to 10,000 times the performance of simulation. Cadence says this option permits design and verification teams to work simultaneously, then runs up to a billion verification cycles overnight.