Cadence and TSMC Team to Accelerate Time-to-Volume for Nanometer Design; Cadence is First Full-Line Distributor of TSMC-Developed Libraries.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Jan. 13, 2003

Taiwan Semiconductor Manufacturing Company, Ltd. ((TSMC) (TAIEX:2330) (NYSE:TSM)) and Cadence Design Systems Inc. (NYSE:CDN) today unveiled their efforts to create an integrated design capability that accelerates customers' time-to-volume for nanometer design. As part of this effort, Cadence becomes the first full-line distributor of TSMC's internally developed standard-cell and I/O libraries, and memories.

In addition, the two companies announced they will collaborate to integrate TSMC's 0.15-micron, 0.13-micron and Nexsys(TM) 90-nanometer (nm) standard cell, I/O libraries and memories with the Cadence(R) Encounter(TM) design flow, which was qualified to be included as part of the TSMC Reference Flow. This provides designers with a new, accelerated path to success for complex nanometer-scale designs. These developments are further supported by the Cadence Design Foundry design services organization, a long-time member of TSMC's Design Service Alliance.

"Our customers face unprecedented challenges with nanometer design, which require us as their design technology supplier to offer new, integrated approaches to both technology and partnerships," said Penny Herscher, executive vice president and chief marketing officer of Cadence. "This next step in our relationship with TSMC provides our customers with integrated products including the foundation IP, design tools, methodologies, and design services they need to be successful. Ultimately, we believe this agreement supports the continued growth of the foundry model critical to so many of our customers."

"Our goal in creating this partnership is to provide our customers with an expanded choice of paths to TSMC silicon," said Dr. Genda Hu, vice president of marketing for TSMC. "Our collaboration with Cadence helps accomplish this goal by integrating our libraries and memories with leading EDA tools, design methodologies, design services, and special function IP. As a market leader and a long-time member of TSMC's Design Service Alliance, Cadence is a natural choice to be the first full-line distribution partner for these libraries and memories."

An Integrated Approach to Nanometer Design

For designers' silicon success at 0.13-micron and below, their design tools and technologies, methodologies, and libraries must work together to model advanced design rules and silicon performance accurately. This requires close alignment and cooperation across the design chain between design technology and silicon manufacturing suppliers. Through existing EDA, IP, and design services partnerships, Cadence and TSMC have invested in collaborative answers to customers' most pressing nanometer design issues, such as signal integrity. The new library distribution partnership between Cadence and TSMC will enable further integration and development for mutual customers.

For example, TSMC's 0.15-micron, 0.13-micron and Nexsys(TM) 90-nanometer standard cell and I/O libraries include enhanced features for SoC design, such as dual-threshold power tuning, that enable designers to integrate high-speed and low-leakage functionality on the same chip. Designers will use TSMC libraries, along with library views for Cadence nanometer design technologies, to implement this in the Cadence Encounter methodology.

TSMC's standard cell and I/O libraries for TSMC's 0.15-micron, 0.13-micron and Nexsys(TM) 90nm processes are available from Cadence now. TSMC's memories will be available from Cadence starting in Q2 2003.

About TSMC

TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced 300mm wafer fabs, five eight-inch fabs and two six-inch wafer fabs. TSMC also has substantial capacity commitments at two joint ventures fabs (Vanguard and SSMC) and at its wholly-owned subsidiary, WaferTech. In early 2001, TSMC became the first IC manufacturer to announce a 90-nanometer-micron technology alignment program with its customers. TSMC's corporate headquarters are in Hsin-Chu, Taiwan. For more information about TSMC please go to http://www.tsmc.com.

About Cadence

Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,200 employees and 2002 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services are available at www.cadence.com.

Cadence and the Cadence logo are registered trademarks and Encounter is a trademark of Cadence Design Systems Inc. All other trademarks or registered trademarks are the property of their respective owners.