Cadence and SynTest Announce Partnership for One Pass Test Synthesis.

Business Editors & High Tech Writers

SAN JOSE and SUNNYVALE, Calif.--(BUSINESS WIRE)--June 5, 2000

SynTest is shipping new products that are fully integrated

with the Cadence Envisia logic synthesis flow --

TurboScan-Ready and TurboDFT-Ready

Cadence Design Systems, Inc. (NYSE:CDN) (San Jose, CA), and SynTest Technologies, Inc. (Sunnyvale, CA), an EDA company and supplier of DFT (design for test) tools for IC designers and foundries, have joined forces to provide a solution for customers who need a one-pass DFT and synthesis solution for multi-million gate system-on-chip (SoC) designs.

The companies have fully integrated Cadence's award winning Envisia logic synthesis tool with SynTest's suite of DFT analysis, BSD (boundary scan design) synthesis and ATPG (automatic test pattern generation) tools. Cadence and SynTest will jointly market the newly integrated DFT solutions.

In addition, as part of the joint agreement between the two companies, SynTest has introduced two new product sets that are integrated with the Cadence Envisia logic synthesis flow -- TurboScan-Ready and TurboDFT-Ready.

According to Cadence's David Silver, Technical Marketing Manager for test and DFT, this partnership will allow Cadence customers who use the attractively priced Envisia logic synthesis tool, in conjunction with Cadence's Synthesis Placement and Routing (SP&R) tools, to also perform automatic insertion of scan chains, followed by compact, high fault coverage ATPG, in one pass.

"This partnership between Cadence and SynTest provides our mutual customers with immediate access to the best DFT and scan synthesis tools available today. SynTest's tools are fully integrated into the Cadence Envisia logic synthesis flow, and are complementary to Cadence's products," said Mr. Silver. "This provides an integrated DFT solution, linked to Cadence's synthesis and layout products."

L.-T. Wang, president and CEO of SynTest, commented, "We are very pleased to have Cadence as a technology and marketing partner. It ties SynTest's TurboScan tool more tightly with Cadence's premier synthesis product and adds a premium backend product that will provide our customers with a complete 'RTL to GDS II' solution and a smooth product design flow. And it does so at lower cost than alternatives."

SynTest's DFT tools support both full- and partial-scan implementations with the same database, and typically generate 30-50% more compact test vector sets with 5-15% higher fault coverage than competing tools.

Price and Availability

The integrated DFT and ATPG tool suites are available immediately from SynTest for the Unix and Linux platforms. TurboScan-Ready is priced at $49,000 (USD) and includes RTL (Verilog or VHDL) DFT and synthesis constraint rule checking, gate-level DFT analysis, automatic testability problem repair and scan selection, reordering and debug capabilities for multiple clock domain designs. TurboDFT-Ready, a more comprehensive package is priced at $99,000 (USD) and also adds embedded SRAM BIST synthesis and automatic boundary scan synthesis (including BSDL file generation). A SynTest ATPG package is available for an additional $99,000 (USD) for customers, who purchase licenses for use of the SynTest bundles with the Cadence tools.

About Cadence

Cadence is the largest supplier of software products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,000 employees and 1999 annual revenue of $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The Company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services may be obtained from the World Wide Web at http://www.cadence.com.

About SynTest

SynTest Technologies, Inc., develops and markets DFT, logic and memory BIST synthesis, boundary scan, ATPG and fault simulation software tools and offers consulting services throughout the world to semiconductor companies, ASIC designers and test groups. The company expects to list its stock in the Taiwan stock market in 2001. More information about the company, its products and services may be obtained from the World Wide Web at http://www.syntest.com.

Acronyms and definition

ASIC:   Application Specific IC
ATPG:   Automatic Test Pattern Generation
BSD:    Boundary Scan Design
BIST:   Built-in-Self-Test
DFT:    Design-for-Test
EDA:    Electronic Design Automation
GDSII   General Data System. This format is used to tapeout or
          produce silicon.
IC:     Integrated Circuit
RTL:    Register Transfer-Level
SoC:    Systems-on-Chip

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