Cadence and Faraday Team to Provide Timing-Driven Design Environment to ASIC Customers.

SAN JOSE, Calif.--(BUSINESS WIRE)--Aug. 18, 1999--

Faraday Adopts Cadence Timing Solution Flow, Envisia Ambit 

Synthesis Tool, and Design Planner to Produce

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Cadence Design Systems, Inc. (NYSE: CDN), the world's leading supplier of electronic design products and services, announces the adoption of its system-level constraint based timing-driven design (TDD) flow at Faraday Technology Corporation, a veteran Taiwan-based professional ASIC design service company. Faraday chose the Cadence(R) TDD flow, including Envisia(TM) Ambit(R) synthesis, Envisia design planner and Envisia Silicon Ensemble(TM) place-and-route ultra, to improve its ability to predictably and consistently meet the tough design and market objectives required by its customers. The Cadence solution enabled Faraday to markedly increase its ability to close on tough timing issues using the timing solution design flow and to boost its synthesis capacity to over a million gates using the Envisia synthesis tool.

This latest project, one of many partnered by Cadence and Faraday, allows Faraday to converge on a trend for chip area and routing delays, the two most critical factors for cost and silicon functionality. Faraday teamed with Cadence methodology services to achieve single pass methodology implementation with no impact to their customers' production schedules. The Cadence timing solution flow, from synthesis to place-and-route, allows the Faraday design centers to accurately predict the area and performance of multi-million gate chips and ensure rapid implementation and timing closure.

"The scale, complexity and process technology of customer chips are moving quickly to the high-end with leading manufacturers focusing on applications in communication, multimedia, PC core-logic and data-processing. In such complex chips, the interconnect delay is the largest concern, so timing convergence and minimizing the number of design iterations are the major concerns of today's sub-micron designer," said Hsiao-Ping Lin, president, Faraday Technology Corporation. "The Cadence TDD flow, from synthesis through place-and-route enables our design centers to have much higher predictability. This increases our ability to guarantee to the customer that we can get their turnaround time met. This is key to keeping Faraday's competitive edge."

"This announcement demonstrates how Cadence technology solutions are helping our customers get a competitive edge in their market. The strength of the individual technologies in the flow -Envisia Ambit synthesis, Envisia design planner, and Envisia Silicon Ensemble place-and-route ultra, delivered in the timing-driven flow, has helped Faraday and a number of other companies achieve a predictable timing convergent design flow," said Bo Cheng, General Manager of Cadence Design Systems Taiwan.

About Cadence

Cadence is the largest supplier of electronic design automation products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With more than 4,000 employees and 1998 annual sales of $1.2 billion, Cadence has sales offices, design centers, and research facilities around the world. The Company is headquartered in San Jose, Calif. More information about the company, its products and services may be obtained from the World Wide Web at http://www.cadence.com.

Cadence, the Cadence logo and Ambit are registered trademarks and Envisia is a trademark of Cadence Design Systems, Inc. All others are properties of their holders.