Cadence and Denali Sign Agreement to Speed Verification of SOC Designs; Denali's Object-Oriented Memory Modeler Uses OMI to Link to Affirma Simulators.

SAN JOSE, Calif.--(BUSINESS WIRE)--May 26, 1999--

Cadence Design Systems, Inc. (NYSE:CDN) and Denali Software, Inc. (Palo Alto, Calif.) today announced an agreement to integrate Denali's Memory Modeler(TM) and Graphical Memory Debugger with the Cadence Affirma(TM) family of hardware description language (HDL) logic simulators.

This integration allows mutual customers to rapidly generate customized memory models increasing functional simulation performance of system-on-a-chip (SOC) designs.

The IEEE 1499 Open Model Interface (OMI) was chosen to link the Memory Modeler to the Cadence simulation products because of its extreme flexibility and extensibility. OMI allows model sharing at any level of abstraction and any OMI compliant model can be executed on any OMI-compliant simulator regardless of the language the model is written in.

The Cadence(R) Affirma simulators have supported OMI-based integration within the Cadence design environment and for third-party tools since June 1997.

"Traditional modeling approaches are failing to meet designers' performance expectations," said Jose Fernandez, director of marketing for system level products for Cadence. "We selected the Denali memory modeling software because it creates unique C language, object-oriented memory models, which provide superior performance and efficiency compared to HDL implementations."

"Verification of complex SOC designs is the biggest challenge that engineers face today," said Sanjay Srivastava, president and chief executive officer of Denali. "Our mutual customers will benefit from having a seamless solution that not only provides high-performance memory models but also helps provide integrated verification methodology for the entire system."

The Denali Memory Modeler will be integrated with the Cadence Affirma SimVision environment, which is the graphical user interface to the Cadence logic simulators. This will provide customers with a smooth integration flow and a uniform look and feel across Cadence simulator products. Cadence customers can also use the Denali models with the Affirma HW/SW verifier to significantly improve co-verification performance of hardware and software components.

"The amount of area occupied by memory in SOC designs is increasing dramatically. This increase leads to the need for sophisticated technologies that improve memory subsystem design. Memory modeling and verification tools and their integration with popular system design and verification tools are important needs that Denali is serving," noted EDA analyst, Rita Glover of EDA Today, L.C. (Phoenix).

About Denali's Memory Modeler

The Memory Modeler utilizes Denali's Specification Of Memory Architecture (SOMA) language to simplify the design of memory architectures and enable distribution of memory components and cores across the Internet and World Wide Web. SOMA uniquely and completely captures the functionality and timing of the memory flow and is used by leading memory developers worldwide.

The Modeler creates memory components for SOC applications and can be tailored to key memory specifications including DRAM, SRAM, SPRAM, SGRAM, DRR, SSRAM, FLASH, PROM, SEPROM AND FIFO memories.

Price and Availability

The Denali Memory Modeler and Debugger are available at U.S. list prices of $5000 and $7000, respectively, and are immediately available from Denali Software.

About Cadence

Cadence Design Systems, Inc. is the largest supplier of software products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products.

With more than 4,000 employees and 1998 annual sales of $1.2 billion, Cadence is headquartered in San Jose, and has sales offices, design centers, and research facilities located around the world. More information about the company, its products and services may be obtained from the World Wide Web at http://www.cadence.com.

About Denali

Denali Software, Inc. offers fast, accurate simulation models for all of the industry's leading memory components and subsystems. Denali's Memory Modeler and SOMA language are used by memory manufacturers to create and verify memory models and make them available over the Internet.

ASIC designers use Memory Modeler and the simulation models to verify complex system-level designs. For more information on Denali's products and services, please see www.denalisoft.com.

Note to Editors: Cadence and the Cadence logo are registered trademarks, and Affirma is a trademark of Cadence Designs Systems, Inc. Memory Modeler is a trademark of Denali Software, Inc All other trademarks are the properties of their owners.