Cadence Validates Test and Diagnostic Flow with Agilent; Encounter Test Successfully Validates Compatibility with Agilent 93000 SOC Series to Address Nanometer Design and Manufacturing Challenges.

SAN JOSE, Calif. -- Cadence Design Systems, Inc. (NASDAQ:CDNS) today announced that the Cadence(R) Encounter(R) Test family of products has been validated on Agilent's 93000 SOC Series automated test system. With this validated test and diagnostic flow between electronic design automation (EDA) and automated test equipment (ATE), joint customers can be confident of higher-quality tests, faster test program creation, and more rapid resolution of yield limiters for their most challenging nanometer designs.

The validation of the test and diagnostics flow enables interoperability through industry-standard formats including Standard Test Interface Language (STIL) and Waveform Generation Language (WGL). This interoperability is critical for a smooth hand-off between the Encounter True-Time Delay Test and Agilent 93000 users and for shortening the time to fully operational production test.

"As a result of our work with Cadence on this important project, our joint customers will have confidence in their test and yield diagnostics flow when they use Encounter Test on the Agilent 93000," said Pascal Ronde, vice president of Agilent's Semiconductor Test Solutions. "This linking of EDA and ATE for test generation and diagnostics removes a significant barrier to meeting critical time-to-market requirements faced by semiconductor companies without such a validated flow."

The collaboration also validated Encounter Diagnostics, which identifies critical design-related issues by analyzing failure data from automated test systems to identify sources of yield loss. This requires full compatibility with the tester to assure that tester failure data efficiently interfaces to Encounter Diagnostics' Chip Pad Pattern (CPP) format.

"This level of interoperability between test generation, ATE and diagnostics will speed our customers' test development time, improve product quality, and shorten yield ramp times," said Sanjiv Taneja, vice president of R&D for Encounter Test at Cadence. "The efforts of Cadence and Agilent demonstrate both companies' commitment to address our customers' needs through a tight collaboration."

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, the Cadence logo, and Encounter are registered trademarks of Cadence Design Systems in the United States and other countries. All other trademarks are the property of their respective owners.