Cadence Ships Cierto VCC Environment For HW/SW Co-design and Reports Customer Successes.

Business Editors

SAN JOSE, Calif.--(BUSINESS WIRE)--Jan. 10, 2000

New Release Provides Links to Co-Verification for

Complete System Design to Implementation Flow

Cadence Design Systems, Inc. (NYSE:CDN), the world's leading supplier of electronic design products and services, today announced worldwide availability of its Cierto(tm) virtual component co-design (VCC) environment for both Unix and Windows NT-based workstations. The production version of the Cierto VCC software is released after extensive validation from more than 15 industry-leading companies who participated in the Felix initiative and early adopter program. The Cierto VCC environment features new productivity-enhancing technology and links to the Cadence(R) Affirma(tm) HW/SW verifier for a complete HW/SW co-development design flow for embedded systems.

The Cierto VCC environment is a key component in the system-on-a-chip (SOC) platform-based methodology pioneered by Cadence to increase productivity and predictability. It enables designers to integrate virtual components representing both hardware and software (HW and SW), explore complex HW and SW tradeoffs, analyze product performance, and evaluate product architectures early in the development cycle. With these capabilities, Cadence strengthens its industry leadership as the only electronic design automation (EDA) company offering production-quality software across the complete HW/SW co-development flow.

New Technology Enhances Productivity and Predictability

The Cierto VCC environment introduces systems designers to new commercially available software estimation techniques, advanced performance modeling, and interface communication synthesis technologies.

--   Cierto VCC environment's revolutionary new software estimation
     technology automatically estimates the performance of embedded
     software using Virtual Processor Models (VPM). This results in up
     to 100 times faster simulation performance compared with
     traditional processor simulation techniques and enables system
     tradeoffs to be considered at the earliest possible stage in the
     design flow.

--   Performance-modeling technology uniquely allows quick and
     accurate evaluation of a function's performance in the context of
     the system. This is accomplished by characterizing execution
     speed using a delay scripting language independent from the
     function, and then using the characterization for performance
     simulation.

--   The new interface communication synthesis technology supports
     both a top-down and a reuse design flow and allows efficient
     mix-and-match of virtual components from various sources. This
     capability helps build a detailed interface between virtual
     components, as well as defines the glue required to connect
     non-matching interfaces.

"It has been more than a decade since the design community has moved up a level of abstraction from gates to the register transfer level. The functional and architectural modeling capabilities introduced with the Cierto VCC environment represent the next step upwards in abstraction and deliver a new front end for system-on-a-chip (SOC) design," said Stan Krolikoski, group director of marketing for system-level products.

Enables Platform-Based Design

The Cierto VCC environment provides software and hardware virtual component vendors with a method for promoting and distributing critical information to ensure successful design and integration of IP blocks for platform-based designs. It allows system companies and silicon vendors to efficiently interact using system-level virtual prototypes, optimize product specifications, shorten development cycles, and capitalize on the increased capabilities offered by multi-million gate integrated circuits.

VCC Products Deliver Customer Results

Through the Felix Initiative leading-edge companies, including ARM, BMW, Debis Systemhaus, Hitachi, Infineon Technologies AG, Magneti Marelli S.p.A, Motorola Semiconductor Products Sector, National Semiconductor Corporation, Nokia NMP, Parades, Philips, ST Microelectronics, Telefonaktiebolaget LM Ericsson, Telelogic SA, and Thomson-CSF have participated in refinement of design methods and technology through ongoing interactions with Cadence. Many of these companies have already had successful results from employing the Cierto VCC environment.

For instance, ARM participated as an early adopter and founding IP provider in the Felix initiative. "ARM partners with industry-leading EDA vendors to enable faster and more accurate routes to system-on-chip solutions," said Alistair Greenhill, EDA business unit manager for ARM. "The VCC environment, together with the recently released links to implementation, supports our ongoing efforts to further enhance the design-in of ARM RISC (reduced instruction set computer) cores into SOC devices and ensures that systems developers have viable solutions for their next-generation ARM Powered products."

Excellent results have also been achieved at Hitachi Micro Systems Europe, Ltd. According to Nobuyoshi Tanimura, managing director, "With the Cierto VCC environment, we have been able to model at a high level of abstraction, components based on our SuperH processor and present virtual components to provide systems solutions for our customers. This enables early hardware/software integration and system verification. Together with the upcoming links to implementation, the Cierto VCC environment will make the design, integration, and exchange of IP significantly easier."

As a systems house, Philips, through its Research and Semiconductors divisions, has been working with Cadence and other partners in the Felix initiative on a project supported by the European Commission through the Esprit/OMI initiative. The objective of this Co-design Simulation and Synthesis (COSY) project, is to develop a system-level design methodology based on commercially available tools and the reuse of IP blocks.

"It appeared that there was a remarkably good fit between the objectives of COSY and the Cadence Cierto VCC environment," said Marinus van Lier, manager system-level design in the Design Technology Group of Philips Semiconductors. "This led to an excellent cooperation, in which Cadence supplied the technology and Philips and the other partners contributed by refining the specifications. This cooperation brought both companies a step forward on the way to our common vision. In the future we will work with structured system design approaches that will enable us to make the right trade-offs and performance evaluations at a very early stage. At the same time this will be a tool to interface with the customer to negotiate the specification."

Tight Links to Co-verification and Complete Design Flow

Cadence is the first provider of a complete flow from system-level design through the validation of system architecture implementation, including interfaces between HW/SW components in the SOC integration. The link between Cierto VCC and the Affirma HW/SW verifier allows the design to be exported at a lower level of abstraction for co-verification of its hardware and software components.

Once the design is fully refined within the Cierto VCC environment, the Cierto environment assembles and generates C code for the software portion of the design and HDL for the hardware portion and then feeds the data to the appropriate tools.

It also provides close integration with leading IP creation languages and technology, such as C, C++, SDL, MatLab, behavioral HDLs, and the Cadence Cierto signal processing worksystem (SPW), with its leading-edge libraries for wireless communications and multimedia applications.

Cadence Augments Services for Co-Development

Cadence offers customers a comprehensive range of services that can help accelerate adoption of a HW/SW co-development methodology and integration of the Cierto VCC product into their existing development environments. The Cierto VCC services package includes tool efficiency training, Quickstart programs, and methodology consulting to recommend a design process that best leverages the Cierto VCC environment.

For more information on Cierto VCC including success stories, data sheets and articles visit http://www.cadence.com/technology/hwsw/ciertovcc/.

Price and Availability

The Cierto VCC environment for systems integrators consists of editors, simulators, estimators, and links to implementation with an U.S. list price starting at $110,000 and is available on Unix-based workstations from Sun Microsystems and Windows NT operating platforms. Initial configurations of the Cierto VCC environment will include a comprehensive package of products and services aimed at building an effective system design. For information regarding international pricing, please contact the local or regional Cadence sales office.

About Cadence

Cadence is the largest supplier of electronic design automation products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With more than 4,000 employees and 1998 annual sales of $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The Company is headquartered in San Jose, Calif. and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services may be obtained from the World Wide Web at http://www.cadence.com.

Cadence and the Cadence logo are registered trademarks and Cierto and Affirma are trademarks of Cadence Design Systems, Inc. All other trademarks are the properties of their owners.