Cadence Sets New Performance/Price Point for Affirma Equivalence Checker and Envisia Ambit Synthesis Product Bundle.SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif.--(BUSINESS WIRE)--May 20, 1999-- High-Performance Synthesis, Formal Verification
In the context of hardware and software systems, formal verification Combination Delivers Cost-effective Approach to Improving Predictability and Productivity of 0.18 Micron SOC Design Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services. http://cadence.com/. See also Verilog. Inc. (NYSE NYSE See: New York Stock Exchange :CDN (Content Delivery Network) A system of distributed content on a large intranet or the public Internet in which copies of content are replicated and cached throughout the network. ) today announced a product bundle that combines the powerful Envisia(TM) Ambit synthesis software with the high-performance Affirma(TM) equivalence checker software. This combination ensures that manual corrections to functionality and timing made during the integrated circuit integrated circuit (IC), electronic circuit built on a semiconductor substrate, usually one of single-crystal silicon. The circuit, often called a chip, is packaged in a hermetically sealed case or a nonhermetic plastic capsule, with leads extending from it for (IC) verification process can be quickly and easily checked reducing overall verification time and improving design productivity. The new product bundle is packaged at the U.S. list price of $175,000. Purchased individually, the two products would cost approximately 20 percent more than the combined package. The Cadence synthesis-formal verification bundle can facilitate exhaustive coverage of critical paths and functional equivalence significantly faster than can be accomplished with traditional gate and register transfer level (RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; ) level simulation. The tool combination can assemble and verify all the synthesized modules, and if timing problems are identified, it can resynthesize the full chip with the built-in Ambit synthesis engine. This ensures functional correctness while providing full-chip timing optimization. Other solutions only allow corrections to be made at the block level delaying timing closure. "Cadence is focused on solving the productivity and predictability challenges of 0.18 micron system-on-a-chip (SOC) design. "This package is targeted at the cost conscious user who needs to confirm small corrections in RTL against manual gate-level edits and make necessary timing corrections without getting bogged down in resynthesis, lengthy simulation runs, or extensive examination of simulation vectors. "This is an easy and effective way to handle urgent, highly visible design issues with less risk," said Peter Hwang, product marketing at Cadence for the Affirma equivalence checker and static verification flow products. Pricing and Availability The product bundle is immediately available on UNIX-based workstations from Sun Microsystems Sun Microsystems, Inc. (NASDAQ: JAVA[3]) is an American vendor of computers, computer components, computer software, and information-technology services, founded on 24 February 1982. and Hewlett-Packard platforms. About Cadence Cadence Design Systems Inc. is the worldwide leader in electronic design software and services. More information about the company may be obtained at www.cadence.com. Note to Editors: Cadence, the Cadence logo are registered trademarks, and Affirma and Envisia are trademarks of Cadence Designs Systems Inc. All other trademarks are the properties of their owners. |
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