Cadence SP&R Solution Used By Crest Microsystems, Inc. For Successful Tapeout of Unique Network ASIC.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Jan. 17, 2001

With SP&R, Crest Quickly Achieved Timing Closure and

Correlation Within Three Percent

Cadence Design Systems, Inc. (NYSE:CDN), the world's leading supplier of electronic design products and services, today announced that Crest Microsystems, Inc. used Cadence(R) SP&R (synthesis/place-and-route) to quickly reach timing closure on a design for a new application-specific integrated circuit (ASIC) for the networking market. Crest Engineers used Cadence Physically Knowledgeable Synthesis (PKS) physical synthesis and Silicon Ensemble(TM) PKS (SE-PKS) optimization place-and-route tools to design and tapeout a very pad-limited design featuring 600 pins and 300,000 gates.

"We would not have been successful in designing this chip without Cadence SP&R," said Jin Hwang, president and CEO of Crest. "We chose the Cadence SP&R design flow because we believe it was the only solution that gives us the full control and delivers timing closure for ASICs using 0.25 micron technology and below. The integrated, front-to-back flow of Cadence SP&R provided better quality of results because of the deterministic results from PKS. The high pin count, large core I/O, and relatively sophisticated clocking requirements made timing closure a real challenge, yet PKS achieved pre- and post-route timing correlation that was within three percent. That's impressive."

For this unique, high-speed ASIC design, Crest used Cadence PKS with the scan-inserted gate-level netlist for placement, global routing, optimization, incremental timing, timing constraints, and correction. Cadence SE-PKS and PKS were used to achieve over 133 MHz performance driven from the top-level constraints among five clock domains in this 300,000 gate ASIC. Key to achieving timing closure was that Cadence SE-PKS automatically prescribed where boundary scan cells resided, as they needed to follow around the I/O frame. In addition, the common timing engines of PKS and SE PKS eliminated iterations, and reduced design time compared with designs done with a different design flow.

"Crest Microsystems joins the fast-growing ranks of satisfied SP&R customers who have accelerated their design cycles and achieved a high quality-of-results for their IC designs," said Jeff Roane, vice president of SP&R marketing at Cadence. "We are gratified to help our customers succeed in their race to market."

Crest Microsystems Inc. provides ASIC design solutions for original equipment manufacturers and chip manufacturers. Crest has the expertise and infrastructure to develop highly integrated devices, such as system-on-a-chip devices, which include processor cores, memories, and other IP.

About Cadence SP&R

Cadence SP&R consists of three products, Ambit(R) BuildGates(R) synthesis, PKS physical synthesis, and Silicon Ensemble PKS optimization place-and-route. This SP&R solution is superior to heterogeneous IC design environments, as it features correlation within three percent through common timing, synthesis, placement, and routing engines used by both logic designers and physical designers.

About PKS Physical Synthesis

PKS is the most complete and tightly integrated physical synthesis solution on the market. It achieves tight correlation with final routed results because its synthesis, timing, placement, and true global routing engines are integrated into the same tool. This integration also provides better quality of results, seen in the frequency and area of the design.

About Silicon Ensemble PKS Optimization Place-and-Route

Silicon Ensemble PKS (SE-PKS) uses Cadence PKS technology to completely restructure gate-level netlists produced by conventional wireload-model-based synthesis. It can also directly read PKS databases that contain placement and global routing information, making it the only place-and-route tool that can accept forward-annotated global routing. SE-PKS is a comprehensive place-and-route tool that incorporates enhanced industry-standard constraint support, which makes it much easier to move designs from conventional synthesis into place-and-route, and to adopt a timing-driven design flow.

Pricing and Availability

Cadence PKS physical synthesis and SE-PKS optimization place-and-route are available for UNIX-based workstations from Hewlett-Packard and Sun Microsystems, and for AIX-based workstations from IBM. One-year U.S. list prices start at $100,000 and $400,000, respectively. For information on international pricing, please contact the local Cadence sales office.

About Cadence

Cadence is the largest supplier of electronic design automation products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,200 employees and 1999 annual revenue of $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products, and its services may be obtained from the World Wide Web at http://www.cadence.com.

Note to Editors: Cadence, the Cadence logo, Ambit, and BuildGates are registered trademarks, and Silicon Ensemble is a trademark of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.