Cadence SP&R Signal Integrity Solution Gains Widespread Support From NEC, Fujitsu, Artisan, Nurlogic, and Virtual Silicon.

Business Editors/High-tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Sept. 20, 2000

Cadence Silicon Ensemble PKS Includes Complete

Solution for Signal Integrity

Cadence Design Systems, Inc. (NYSE:CDN), the world's leading supplier of electronic design products and services, today announced the widespread adoption by NEC and Fujitsu of the Cadence(R)Silicon Ensemble(TM)solution with signal integrity (SI) capabilities. The company also announced strong library support for the Cadence SP&R (synthesis/place-and-route) solution for SI problems from companies including Artisan Components, Inc., Nurlogic Design, Inc., and Virtual Silicon Technology, Inc. This library support is based on processes from leading semiconductor foundries including United Microelectronics Corp. (UMC).

The newest release of Cadence Silicon Ensemble, Silicon Ensemble PKS (SE-PKS) optimization place-and-route, includes physically knowledgeable synthesis (PKS), and is a complete solution for SI prevention and correction. SI is of major concern for integrated circuit (IC) designs of 0.18 micron and below.

Kiminori Fujisaku, general manager of World Wide System LSI Technologies of Fujitsu Electronic Devices Group, stated, "We have enjoyed a close working relationship with Cadence, and are very comfortable with this mature technology that is production proven. The Cadence signal integrity solution was easy to adopt, because our IPSymphony, System LSI integrated circuit environment, supports Silicon Ensemble in the flow. Silicon Ensemble is well enhanced to provide SI capability for prevention, analysis and correction of crosstalk in DSM designs."

"Cadence's signal integrity solution enables our ASIC customers to get higher quality of results by eliminating the need to over-constrain designs for preventing SI problems," stated Nobuyuki Nishiguchi, senior manager, Design Methodology Group, System LSI Design Engineering Division, NEC Electron Devices. "The excellent support that we have received from Cadence has prompted us to adopt their Signal Integrity solution, which will allow us to provide a premium design flow that differentiates our customers."

Cadence Silicon Ensemble-PKS with SI Capabilities

With shrinking process geometries and rising clock frequencies, it is essential for designers to address signal integrity problems to meet timing closure. It is impossible to design and meet timing closure without considering crosstalk (interference caused by the close proximity of wires). An integral part of the SP&R solution, SE-PKS offers a holistic approach to correcting signal integrity by addressing the most comprehensive set of effects including: crosstalk, voltage drop, wire self-heat, hot electron, and electromigration. SE-PKS automatically prevents and corrects signal performance, timing, and design reliability failures during chip layout.

The Cadence SP&R approach is an implementation solution that promotes SI awareness throughout all the phases of the design cycle. Algorithms work concurrently from synthesis down to detailed routing. The physical implementation and SI analysis go hand-in-hand throughout the flow, which includes various unique techniques to prevent SI issues from developing. In the cases where prevention is not possible, SE-PKS determines automated ways of correcting the problems without disturbing other design parameters. Through strong correlation, SE-PKS eliminates front-to-back iterations, thereby enabling timing closure.

"Demand for our SI solutions from worldwide, leading-edge technology companies and ASIC vendors such as NEC and Fujitsu, demonstrates that Cadence SP&R delivers best-in-class design to its end users," commented Jeff Roane, vice president of SP&R marketing at Cadence. "Strong customer demand has resulted in complete library support for Cadence SI technology from Artisan Components, Nurlogic, and Virtual Silicon."

Mark Templeton, president and chief executive officer at Artisan Components, Inc., a leading provider of high-quality silicon intellectual property, confirmed, "Artisan is committed to provide libraries supporting Cadence's signal integrity flow to our worldwide customers. We are seeing a very strong demand for a signal integrity analysis tool as our customers scale to processes below 0.18 micron. We believe that Cadence provides the most complete solution addressing these needs."

About Cadence SP&R

Cadence SP&R consists of two products, Envisia(TM) PKS physical synthesis and Silicon Ensemble PKS (SE-PKS) optimization place-and-route. This SP&R solution is superior to heterogeneous IC design environments, as it produces perfect correlation through common timing, synthesis, placement, and routing engines used by both logic designers and physical designers.

About Silicon Ensemble PKS Optimization Place-and-Route

SE-PKS contains state-of-the-art signal integrity analysis, prevention, and correction capabilities. SE-PKS uses Cadence PKS technology to completely restructure gate-level netlists produced by conventional wireload-model-based synthesis. It can also directly read Envisia PKS databases that contain placement and actual global routing information, making it the only place-and-route tool that can accept forward-annotated global routing. SE-PKS is a comprehensive place-and-route tool that incorporates enhanced industry-standard constraint support, which makes it much easier to move designs from conventional synthesis into place-and-route, and to adopt a timing-driven design flow.

Pricing and Availability

Cadence SE-PKS optimization place-and-route is available for UNIX-based workstations from Hewlett-Packard Company and Sun Microsystems, and for AIX-based workstations from IBM. One-year U.S. list price starts at $400,000. For information on international pricing, please contact the local Cadence sales office.

About Cadence

Cadence is the largest supplier of electronic design automation products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,100 employees and 1999 annual revenue of $1.1 billion, Cadence has sales offices, design centers, and research facilities located around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. For more information, visit http://www.cadence.com.

Note to Editors: Cadence and the Cadence logo are registered trademarks, and Envisia and Silicon Ensemble are trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.