Cadence Lengthens Lead in Signal Processing; SPW Upgrade Strengthens Vision for Design and Development of Algorithmic-Intensive DSP and Communications Systems.

Business Editors/High Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--May 30, 2001

Cadence Design Systems, Inc. (NYSE:CDN), the world's leading supplier of electronic design products and services, today announced an upgrade to its Signal Processing Worksystem (SPW). With its current enhancements, Cadence(R) SPW 4.7 retains its exclusive position as the only system-level, hierarchical block-diagram design solution with an optimized flow for implementation. SPW provides a fully integrated solution from algorithm design to implementation on a SoC or multi-ASIC/FPGA system.

With this new release, SPW includes an improved NC-Cosim link with the ability to test multiple register transfer level (RTL) instances, and a new link with the Ambit(R) BuildGates(R) data path optimizer (Verilog) that results in faster, smaller gate-level designs without manual intervention. Automatic HDL import for block wizard improvements and new application-specific library updates for WCDMA and GSM/EDGE round out the latest Cadence signal processing software offering. SPW continues to reduce development time by improving code import technology for sources coming from C, C++, SystemC, MATLAB, VHDL, or Verilog, and providing optimized links for implementation. It also keeps pace with standards through ongoing library updates.

"Cadence is committed to improving the entire design flow with new and/or improved technology links," said Rahul Razdan, corporate vice president and general manager of Systems and Functional Verification at Cadence. "This upgrade is further evidence of our commitment to wireless, wired, multimedia, and consumer electronics solutions. SPW continues to play an important role in our system-level design flow and includes extensive capabilities for creating market-differentiated parameterized IP."

The improvement to the SPW/NC-Sim technology link (NC-Cosim) allows designers to have multiple devices under test (DUT). This innovation is made possible for the first time with the improved NC-Sim multi-DUT approach. The SPW/Ambit BuildGates with datapath option link increases productivity and performance designs. It also provides automatic generation of datapath-friendly RTL through the SPW/HDS interface. With this release, the SPW block wizard now features automatic RTL import.

Library updates are validation of the participation of Cadence in standards bodies. WCDMA library was updated to comply with the latest standard. The 3GPP library was enhanced to conform to version 3.4.0 specifications. The GSM library includes the EDGE standard under which the ECSD system was optimized. This includes all coding schemes (MCS-1 through MCS-9).

Price and Availability

Available immediately, the SPW2000 signal processing worksystem is $22,000 for a one-year license. SPW 4.7 supports the Forte 6.1 compiler and runs on Sun Solaris 2.7, Solaris 2.8, and HP-UX 11 platforms.

About Cadence

Cadence is the largest supplier of electronic design automation products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With 5,700 employees and 2000 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products, and services is available at www.cadence.com.

Note to Editors: Cadence, Ambit, BuildGates, and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.