Cadence Joins Synopsys' Tap-in Program as First Design Constraints Licensee; Top Two EDA Companies Work Together to Enable Interoperability.MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 4, 1998--Synopsys Inc. (NASDAQ NASDAQ in full National Association of Securities Dealers Automated Quotations U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on :SNPS SNPS Space Nuclear Power System ), today announced that Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services. http://cadence.com/. See also Verilog. Inc. (NYSE NYSE See: New York Stock Exchange :CDN (Content Delivery Network) A system of distributed content on a large intranet or the public Internet in which copies of content are replicated and cached throughout the network. ) has joined their technology access program, TAP-in(TM), as the first company to license the Synopsys Design Constraints (SDC SDC Silver Dollar City SDC Security Door Controls SDC Student Development Center SDC San Diego Chargers SDC Science Data Center SDC System Development Charges SDC Studebaker Drivers Club SDC San Diego, California (border patrol sector) ) format. Under the terms of the agreement, Cadence has licensed the SDC format in addition to the popular Liberty(TM) format -- both available through the TAP-in program. With the addition of Cadence as the eleventh member to join TAP-in, licensees now constitute nearly 95 percent of the EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. market revenue, including the six largest EDA vendors. "Participating in the Synopsys TAP-in program is another step forward in our openness strategy," said K.C. Murphy, Cadence executive vice president, strategic business group and corporate strategic planning Strategic planning is an organization's process of defining its strategy, or direction, and making decisions on allocating its resources to pursue this strategy, including its capital and people. . "Cadence believes that interoperability is a key component of next-generation design flows, and this belief led us to work with Synopsys to define the commands to be included in this design constraint license format. Making these formats available will accelerate the industry's progression toward timing-driven design." "We are very pleased to welcome Cadence into the TAP-in program," said Paul Lippe, senior vice president of business and market development at Synopsys. "Our mutual customers will now have access to our widely used library and design constraint formats. In the spirit of openness, Synopsys is also looking forward to working with Cadence to define the commands for their LEF LEF Life Extension Foundation LEF Leading Edge Forum (CSC) LEF Local Education Funds LEF Literacy Empowerment Foundation LEF Library Exchange Format (Cadence Design Systems) and DEF APIs. With market leaders such as Cadence participating in the TAP-in program and creating a similar program of their own, it is a clear sign that the industry is making significant steps in achieving better tool interoperability." About Synopsys Design Constraints Synopsys Design Constraints are widely used to describe designer intent for deep submicron designs and include constraints for timing, clock, area, test and power in addition to other environmental and operating conditions. Design constraints drive a variety of EDA tools including synthesis, timing analysis and place and route. They are a key input to logic synthesis The conversion of a high-level electronic circuit description into a list of logic gates and their interconnections, called the "netlist." Every logic synthesis program understands some subset of Verilog and VHDL. -- Synopsys' Design Compiler(TM) and the PrimeTime(TM) static timing analysis tool. By providing a common method to describe design intent, Synopsys is addressing the industry's need to simplify the key design challenge of timing closure. Timing assertions, one component of Synopsys Design Constraints, will allow designers to use the identical files to drive synthesis and place and route. This ability to identically interpret design intent should help place and route tools to realize a design much closer to that predicted by the synthesis tools, reducing costly iterations and accelerating timing closure. "I am encouraged by this strong degree of cooperation between Cadence and Synopsys," said Gadi Singer, general manager, Design Technology at Intel and chair of the EDA Industry Council. "EDA customers can benefit significantly from the increased degree of EDA interoperability created as a result of leaders such as Cadence and Synopsys openly sharing their widely used formats that are common to many design flows." "I fully support this significant move by Synopsys which has enabled the EDA industry to have access to its design constraints format," said Dr. Hitoshi Yoshizawa, chief manager, System ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. Division at NEC (NEC Corporation, Tokyo, www.nec.com, www.necus.com) An electronics conglomerate known in the U.S. for its monitors. In Japan, it had the lion's share of the PC market until the late 1990s (see PC 98). NEC was founded in Tokyo in 1899 as Nippon Electric Company, Ltd. . "Now, because of this, Cadence can drive timing in its tools straight from these constraints format files. The outcome of this agreement helps narrow the so-called design productivity gap -- which is something the electronics industry has waited a long time for." About Synopsys' TAP-in Program The TAP-in program was designed to advance EDA tool interoperability through technology exchange and licensing, allowing open and easy access to Synopsys' widely used formats. The basis for TAP-in is to make important formats available quickly with appropriate support and updates. Licensing is open to all interested industry parties, including EDA companies  The external links in this article or section may require cleanup to comply with Wikipedia's content policies. , semiconductor, IP and library vendors, industry
organizations and universities. Through TAP-in, partners have access to
Liberty, the most widely used library format in the electronics design
industry today, in addition to the Synopsys Design Constraints format
which was announced at the Design Automation Conference in June of 1998.Pricing Synopsys is providing enhanced interoperability in the industry and prefers to trade access to formats in lieu of the licensing fee. However, if a company wishes to purchase a Liberty or SDC license, they are available to new licensees at a list price of U.S. $95,000. Additionally, current Liberty licensees are eligible for discounts on other licensed Synopsys formats. About Cadence Cadence Design Systems, Inc. provides comprehensive services and technology for the product development requirements of the world's leading electronics companies. Cadence is the largest supplier of software tools and professional services (job) professional services - A department of a supplier providing consultancy and programming manpower for the supplier's products. used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics and a variety of other electronic-based products. With more than 4,400 employees and annual sales of $916 million in 1997, Cadence has sales offices, design centers and research facilities around the world. The company is headquartered in San Jose San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif., and traded on the New York Stock Exchange New York Stock Exchange (NYSE) World's largest marketplace for securities. The exchange began as an informal meeting of 24 men in 1792 on what is now Wall Street in New York City. under the symbol CDN. More information about the company and its products and services may be obtained from the World Wide Web at http://www.cadence.com. About Synopsys Synopsys Inc. (NASDAQ:SNPS), is a leading supplier of electronic design automation (EDA) solutions to the global electronic market. The company provides comprehensive design technologies to creators of advanced integrated circuits Integrated circuits Miniature electronic circuits produced within and upon a single semiconductor crystal, usually silicon. Integrated circuits range in complexity from simple logic circuits and amplifiers, about 1/20 in. (1. , electronic systems and systems on a chip. Synopsys also provides consulting services and support to its customers to streamline the overall design process and accelerate time-to-market. Additional information about Synopsys is available at http://www.synopsys.com. Note to Editors: Synopsys is a registered trademark of Synopsys Inc. TAP-in, Liberty, Design Compiler and PrimeTime are trademarks of Synopsys Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
CONTACT: Synopsys Inc.
Amy Attard, 650/694-1653
amya@synopsys.com
or
Cadence Design Systems, Inc.
Laurie Stanley, 408/428-5019
las@cadence.com
or
The Hoffman Agency
Ellie Katsoudas, 408/975-3057
ekatsoudas@hoffman.com
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