Cadence First Encounter Selected by ST for 90 Nanometer System-on-Chip Design.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Feb. 3, 2003

Cadence Design Systems, Inc. (NYSE:CDN) today announced that STMicroelectronics has selected Cadence(R) First Encounter(R) for silicon virtual prototyping of its system-on-a-chip (SoC) designs at 90 and 130 nanometer silicon geometries. The company will use First Encounter, a key nanometer technology included in the Encounter platform, to ensure design success and shorten time-to-market on very complex integrated circuits.

At nanometer geometries, interconnect plays a vital role in determining chip performance. ST design engineers will use First Encounter to quickly generate and rapidly refine an accurate virtual prototype of their IC physical design, including its interconnect. The prototype provides fast feedback on chip performance and a fully functional, physically feasible layout. This in turn will help ST's design teams produce a signoff-quality floor plan and preliminary placement optimized for rapid, reliable design closure.

Using First Encounter will help ST continue to stay ahead of their competitors in delivering leading-edge, high-value products to their customers and allows ST to define a new interface with ASIC customers. First Encounter will be used to drive both Cadence and third-party tools for detailed chip implementation.

"ST is moving aggressively to leverage cutting-edge silicon technologies and design methodologies," said Ping Chao, senior vice president and general manager of the Digital IC group at Cadence. "We're pleased to have been selected for this advanced design flow. First Encounter quickly establishes a physically feasible design approach, enabling users to complete even demanding designs rapidly and predictably."

"Our evaluations indicated the First Encounter approach has clear advantages, especially at nanometer geometries," said Philippe Magarshack, group vice president for Design Automation, Central Research and Development at STMicroelectronics. "The silicon virtual prototype produces realistic views of the chip in a shorter time than other methods we've seen, significantly speeding up the physical design flow."

About Cadence

Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics based products. With approximately 5,300 employees and 2002 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.

Cadence, the Cadence logo, and First Encounter are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.