Cadence Extends SOC Technology Leadership With New Integration Ensemble and Unveils SuperChip Initiative.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--Feb. 26, 2001

IE Represents Genesis SP&R Solution, a Key Deliverable of

Cadence's SuperChip Initiative, Which Addresses Convergence of RF,

Analog, and Digital on a single SOC

Cadence Design Systems, Inc. (NYSE:CDN), the world's leading supplier of electronic design products and services, today introduced the Cadence(R) Integration Ensemble(TM) (IE) hierarchical integrated circuit (IC) implementation tool for designing complex systems-on-chips (SOCs). IE is the next generation of the Cadence SP&R (synthesis/place-and-route) solutions and a major step in the Cadence SuperChip Initiative, the company's long-term technology roadmap, also introduced today.

Cadence pioneered the industry's first physical synthesis solution, Cadence Physically Knowledgeable Synthesis (PKS), in September of 1999, and with the introduction of Silicon Ensemble(TM) PKS (SE-PKS) in March 2000, provided the industry's first and only integrated SP&R solution. IE represents the industry's next-generation SP&R solution that runs from register transfer level (RTL) to GDSII on a single database with single synthesis, placement, timing, and routing engines. Cadence developed IE in collaboration with a number of customers, through the Nano and Cadence database projects, to handle designs of more than 25 million gates and process geometries of 0.12 micron and below.

There are many unique innovations in IE, including its being the industry's first and only fully integrated, hierarchical, timing driven SOC design system. IE's novel timing abstraction capabilities speed synthesis, timing, and design closure. IE includes third generation dynamic floorplanning functions that help to produce optimal floorplans. The IE system is built on a new, ultra-high capacity and high performance SOC database, capable of handling designs of more than 25 million gates extremely effectively. The database provides a common platform for unparalleled integration of synthesis, placement, routing, timing analysis, power analysis, and signal integrity analysis.

"At STMicroelectronics, we have ever increasing need for timing predictability, capacity, and performance from EDA tools for our multimillion gate mixed analog-digital SOC class designs," said Philippe Magarshack, vice president, Central R&D Group, Design Automation, STMicroelectronics. "We have worked very closely for the past year and a half with Cadence to address this requirement. As a result of our co-development work using IE, we have built a more predictable and reliable IC design environment. We are happy to see that IE has proven its capacity and performance on multimillion-gate SOC designs. We have successfully used IE and its integrated hierarchical database to design and tape-out a multi-million transistor chip in our 0.12 micron technology. We are now putting IE in use for production mixed analog-digital designs of up to 100 million transistors in this same 0.12 micron technology."

According to Yoshio Okamura, department manager, Design Technology Development Department, System LSI Business Division, Semiconductor and Integrated Circuits, Hitachi, Ltd., "We selected IE for our high-speed SOC designs mainly for its ultra high capacity single database. IE creates a unified chip implementation platform for multimillion gate designs. We believe that IE gives us a strategic advantage in meeting our design goals and time-to-market windows."

New Cadence SuperChip Initiative

The Cadence SuperChip Initiative is the company's roadmap for a comprehensive design technology suite and methodologies that spans the design of the next generation of systems, ICs, printed circuit boards (PCBs), and embedded software. Key development areas include integrating hardware and software design, integrating digital, analog and RF design, integrating custom and semi-custom design styles, and integrating silicon-to-package-to-board design.

The communications market is driving a significant increase in analog and RF content, and a need for it to come together with high speed digital, all on a single chip. One of the first focus areas is bringing together Cadence's industry leading analog, RF, and mixed-signal custom SOC products with its industry leading SP&R products, including Integration Ensemble. Another key initial deliverable of the SuperChip Initiative will include AMS Designer, a unified functional verification system for analog, digital, RF, and mixed-signal SOCs.

The SuperChip Initiative features a unique product development model under which major customers collaborate with Cadence to develop advanced products. Cadence customer Texas Instruments (TI), the leader in communication ICs, is an initial partner for the product development featured in this Initiative. The TI development project will enable the convergence of complex analog, digital, mixed-signal, and RF circuits on SOC designs. These chips help fuel the electronics revolution in the communications and consumer electronics markets.

"TI is collaborating with Cadence because it has the most comprehensive EDA solutions for analog and mixed-signal integrated circuit design, and the commitment to leverage these technologies into a next-generation mixed-signal system-on-chip design system," said Felicia James, Mixed Signal Product Development EDA Manager of Texas Instruments. "As the initial key customer in the Cadence SuperChip Initiative, TI will be able to increase its competitive advantage in mixed-signal SOC designs and continue to affirm its position as the world's leader in analog and mixed-signal integrated circuits."

"The delivery of Integration Ensemble and the unveiling of the SuperChip Initiative represent critical solutions to help solve our customers' SOC design needs, and are a testament to our technology leadership," said Ray Bingham, president and CEO of Cadence. "In fact, these solutions are being co-developed with a number of our customers. This model of collaboration is vital in bringing major innovations such as IE and SuperChip to market."

IE Price and Availability

IE is available for limited release on UNIX-based workstations. The one-year U.S. list price for a time-based license (TBL) starts at $600,000. For information on international pricing, please contact a local Cadence sales office.

About Cadence

Cadence is the largest supplier of electronic design automation products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,400 employees and 2000 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The Company is headquartered in San Jose and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services may be obtained from the World Wide Web at www.cadence.com.

CADENCE INTRODUCES INTEGRATION ENSEMBLE AND

ITS SUPERCHIP INITIATIVE

Addendum

Integration Ensemble Features and Benefits

Cadence(R) Integration Ensemble(TM) addresses today's biggest IC design challenges -- timing convergence, capacity, and turn-around-time -- with a single, easy-to-use interface, and common database and timing engines. IE features next-generation hierarchical design implementation algorithms in an automated, integrated flow that provides comprehensive capabilities for RTL to GDSII design. This directly translates into more designs per engineer per year.

IE is the only tool available today that provides a complete, integrated, front-to-back design solution. IE is fully compatible with Cadence's existing SP&R products, and offers an easy migration path from these tools.

Along with industry-standard Cadence Silicon Ensemble(TM) PKS technology, IE offers many advanced features, such as support for multi-supply designs, hierarchical signal integrity prevention and analysis, and full chip integration and assembly for designs of 0.12 micron or below. To achieve predictability and best-in-class, RTL-to-GDSII, design flow for nanometer designs, IE supports the following features:

--  Next-Generation Common Database for Entire Flow Delivers High
    Capacity, High Performance, High Predictability -- IE is built on
    a Genesis database that provides unprecedented capacity, handling
    twenty-million-plus gates. The uniform database eliminates a need
    for data transfer between different tools, such as LEF/DEF
    translation, improving turnaround time by 10X. The single database
    is 2-10X smaller than earlier databases, such as DFII and Pillar.
    Logical and physical views are stored and shared in the database,
    reducing the need for logical-to-physical iteration and, it has
    improved ECO support for last minute changes. Quality-of-results
    and a high degree of predictability is achieved through concurrent
    synthesis and placement. A single database makes constraints and
    files management easier.

--  Dynamic Timing Abstraction Reduces Memory Use, Improves Runtimes
    -- IE uses innovative shell/core partitioning and Dynamic Timing
    Abstraction technology to meet timing constraints. Dynamic Timing
    Abstraction reduces memory usage and improves run times. This
    algorithm alone provides 2X faster chip level timing analysis and
    capacity.

--  Front-to-back Common Timing Engine Delivers High Performance and
    Capacity -- IE includes an incremental hierarchical static timing
    analysis engine. The Common Timing Engine is a full chip timing
    analysis engine that supports SPEF and DSPF formats. It supports
    sophisticated constraints and exceptions, such as "to" and
    "through" pin support, false paths, multi-cycle paths,
    cycle-stealing, multiple clock waveform specs, and
    user-customizable timing reports.

--  Dynamic Floorplanning Provides Accurate Timing Correction -- At
    the top level, IE uses shell/core partitioning for automatic
    budgeting and global buffer insertion for timing correction. IE
    floorplanning fully support blocks, pins, bus/bundle(s), and
    repeater insertion.

--  Cadence Chip Assembly Router Provides Improved Wire Editor -- IE
    includes the industry-proven Cadence Chip Assembly Router
    technology for wire editing, bus editing, and push/shove
    capability.

--  New Power Router is Specially Tuned -- IE has a brand new power
    routing system, specially tuned to suit six-plus metal layer
    design, both hierarchical and flat. Power routing in IE supports a
    single via generation and via merging functionality.

--  Multi-supply Voltage Support Allows Interactive and Automatic
    Power and Ground Assignment.

--  Graphical User Interface (GUI) is Intuitive -- IE has an
    integrated, easy-to-use, graphical user interface. Unlike
    traditional GUIs oriented towards menu-driven tool control, the
    GUI in IE uniquely combines linked graphical and text views. This
    speeds access to design information, making for more productive
    design debug.

Note to Editors: Cadence and the Cadence logo are registered trademarks, and Silicon Ensemble and Integration Ensemble are trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.