Cadence Extends IC Technology and Market Leadership With Silicon Ensemble; Breakthrough place-and-route solution addresses fab capacity crisis, system-on-a-chip design.

SAN JOSE, Calif.--(BUSINESS WIRE)--Jan. 15, 1996--Targeting the increasing challenges of locating silicon fab capacity and designing more content into single chip, Cadence Design Systems, Inc. today introduced the Silicon Ensemble(TM) place-and-route system for designing multi-layer metal integrated circuits (ICs).

An extension to its market-leading IC place-and-route product line which pioneered the capability to design with 3-plus layers of metal, Silicon Ensemble builds upon the company's current 90% share of this market with a tool containing a new collection of application-specific placement and routing engines for complex system-on-a-chip design.

Cadence pioneered the 3-plus layer approach to IC design with Cell3 Ensemble(TM) in 1991. Close to 4,000 multi-layer designs have been produced using Cadence tools, including almost 1,000 chips that contain 4, 5, and 6 layers of metal.

Cadence once again breaks new ground with Silicon Ensemble. Built upon that unmatched production-proven experience and based on the innovative FlexChip(TM) architecture, Silicon Ensemble offers a comprehensive suite of new place-and-route technologies targeting future processes as fine as .18 micron.

The solution delivers the benefits of Cadence's unique "area architecture" approach to multi-layer IC designers and improves the efficiency and ease-of-use of submicron, multi-layer processes.

"The capacity fluctuations and growing process complexities that characterize today's IC market dictate that state-of-the-art technology for silicon design can no longer be used only by leading-edge designers. With Silicon Ensemble, we are delivering a place-and-route system that will immediately benefit 70-80% of the market," said Tom Katsioulas, director of product marketing at Cadence.

"And, the new capabilities introduced as part of the Silicon Ensemble system provide leading-edge designers with the technology they need to pack more system-level functionality onto a chip."

"Exponential Technology is developing one of the fastest microprocessors in the world, thanks in part to the advanced IC design technology from Cadence," said George Taylor, chief technology officer at Exponential Technology.

"Our design uses four-layer routing and specialized layout styles for datapath and control blocks. Advanced capabilities such as Cadence's area routing technology have enabled us to design the chip with unprecedented density."

FlexChip for extended area routing

Cadence's FlexChip architecture extends place-and-route technology to a new level. It consists of a collection of application-specific placement and routing engines and enables a broader approach to deliver the advanced technology of area routing with the ease-of-use characteristic of channel approach.

As a result, FlexChip delivers a mature physical IC implementation solution to designers working with advanced processes for the first time. Through efficient mixed block and cell layout, simplified sub-micron timing, a comprehensive clock solution, intelligent power routing, advanced interconnect analysis, and Windows-compliant user interface, the FlexChip architecture provides an unmatched combination of technology and usability for system-on-a-chip design.

Part of Cadence's complete solution for systems in silicon

Cadence offers a complete portfolio of design technology for advanced silicon design. Silicon Ensemble is the third major component introduced in the past 18 months as part of an integrated suite of tools. The offering also includes SiliconQuest(TM) for high-level design planning and estimation and Silicon Synthesis(TM) for advanced timing optimization. The company also offers an array of professional design services, including IC design outsourcing, to complement its market-leading technology offering.

Pricing and Availability

Silicon Ensemble is available in two configurations starting at $265,000 U.S. list price. The base configuration offers advanced FlexChip architecture features for 2-3 layer design, with SmartPath and advanced clock generation options available. Silicon Ensemble DSM (Deep Sub-micron) includes the same FlexChip features and options, plus RC extraction, but is optimized for 2-to-n layer design, and offers the Xtalk intelligent router as an additional option.

Cadence Design Systems, Inc. is the worldwide leader in the development and marketing of design automation software and services that accelerate and advance the process of designing electronic systems. Cadence combines leading-edge technology with a complementary set of services that enables customers to improve the quality and time-to-market performance of innovative electronic products.

Cadence is based in San Jose, Calif., with research and development, sales and support locations throughout the world. The company is listed on the New York Stock Exchange under the symbol CDN. -0-

Note to Editors: All Cadence products referred to are trademarks of Cadence Design Systems, Inc.

CONTACT: Cadence Design Systems, Inc.

Mike Sottak, 408/428-5036

[e-mail]