Cadence Enhances Virtuoso Platform with New Chip Integration Solution for Fast, High-Performance Custom Design.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--March 1, 2004

New Flow Offers 10x Performance Improvement and Reduces Time for

Full-Scale Physical Integration by Half

Cadence Design Systems, Inc. (NYSE:CDN) today announced that it has optimized its Virtuoso(R) custom design platform with the availability of a new chip integration flow, coupled with the newest release of its Virtuoso Chip Editor. By using these solutions together, designers will, for the first time, be able to perform full-scale physical integration across multiple design domains, including analog, custom digital, RF, memories/arrays, and digital standard cells from a full custom point of view.

This new generation Cadence(R) technology offers up to more than 10 times performance improvement over existing custom design solutions. It is also capable of shortening physical design integration from one month to approximately two weeks in a typical advanced mixed-signal design with over 1.5 million transistors.

Cadence's chip integration flow and Virtuoso Chip Editor provide designers an automated physical design integration solution from floorplanning through chip finishing and tape-out, resulting in significant productivity gains and faster time-to-market. Building upon Cadence's commitment to drive open collaboration for its customers, the new chip integration solution provides a seamless bi-directional integration path to and from the Cadence Encounter(TM) digital IC design platform through the OpenAccess database.

"The industry needs flows and tools which address the lack of interoperability that hinders the speed at which complex SoCs have to be produced," said Steve Schulz, president and CEO of the Silicon Integration Initiative (Si2). "The fact that the new Cadence chip integration flow and Virtuoso Chip Editor are based on OpenAccess offers designers greater flexibility and faster SoC assembly across multiple design environments."

"The chip integration flow is a key component of the Virtuoso platform and it is the first of its kind in the industry enabling semiconductor manufacturers to bring multiple design domains together into a single chip implementation," said Felicia James, vice president and general manager of the Cadence Virtuoso custom IC design platform. "With this advanced custom design flow, customers can resolve the challenges in designing mixed-signal ICs so that first-pass silicon can be achieved much faster and with greater predictability."

Enhanced Platform Features

The Cadence Virtuoso platform is integrated with the Cadence Encounter platform through OpenAccess, ensuring interoperability between custom and digital design environments. This versatility enables the right solution to be applied to the right design task. The chip integration flow also builds upon the OpenAccess database, allowing the full custom designer a clear, seamless integration path into the digital design environment.

In addition, Cadence is releasing an enhanced version of its Virtuoso Chip Editor -- version 3.3 -- to further increase layout productivity. Highlights of version 3.3 include immediate visual feedback on design rule violations and advanced connectivity awareness that speeds up chip finishing by alerting the user of accidental opens and shorts. Virtuoso Chip Editor 3.3 offers more efficient editing of full-chip finishing tasks.

Supported by robust design tools and a "meet-in-the-middle" methodology that combines the speed of top-down design with the silicon accuracy of bottom-up design, Cadence's new chip integration flow embodies the critical elements required to successfully develop mixed-signal custom designs. This includes the capability to bi-directionally pass data between multiple design domains, floorplanning capability to facilitate top-down and bottom-up design early on, analog routing capability to facilitate continuous evolution, early and frequent parasitic and analysis capability, and chip finishing capability for large design databases.

Pricing and Availability

The new Cadence chip integration flow and Virtuoso Chip Editor are available immediately on HP, Sun, IBM, and Linux platforms. The detailed, step-by-step flow is based on a distributable 15 million-transistor Ethernet switch and Process Design Kit (PDK). Free workshops about the new flow and Virtuoso Chip Editor will be available in March.

U.S. pricing for a one-year license of the Virtuoso Chip Editor starts at $40,000. Specific operating system support varies by product.

About Cadence

Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 4,800 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.

Cadence and the Cadence logo are registered trademarks, and Virtuoso and Encounter are trademarks of Cadence Design Systems, Inc. in the U.S. and other countries. All other marks are properties of their respective holders.