Cadence Design Systems and Mentor Graphics Team to Deliver New Hardware/Software Co-Development Flow.

Business Editors/High-Tech Writers

BOSTON--(BUSINESS WIRE)--Sept. 4, 2001

Cadence Design Systems, Inc. (NYSE:CDN) and Mentor Graphics Corp. (Nasdaq:MENT) today announced the availability of an integrated hardware/software (HW/SW) co-development flow. The integrated HW/SW co-design and verification flow facilitates faster design times, testbench re-use, and a continuous flow from system-level verification to implementation for improved accuracy.

The Cadence(R) Virtual Component Co-Design (VCC) environment for HW/SW co-design now connects to the Mentor Graphics(R) Seamless(R) Co-Verification Environment(TM) (CVE(TM)) for HW/SW co-verification. Tight integration of the two solutions is possible through open modeling infrastructures, which the two companies produced in response to customer requests for a joint solution.

"As a leader in silicon system design, Philips Semiconductors needs a smooth design flow with direct connections between co-design and co-verification tools as an essential component to success," said Marinus van Lier, Design Technology Group, Philips Semiconductors. "Cadence VCC provides us with the functionality to interact within the design chain at the earliest possible point in time. Decisions made at the system level need to be confirmed later on and the direct link to Mentor Graphics Seamless allows efficient design transfer to implementation."

Integrated Design and Verification Co-Development Flow

Using the integrated co-development flow, designers apply the system-level design space exploration features in the Cadence VCC environment. In addition, designers confirm critical architectural decisions, such as the hardware and software partitioning of system functionality, early in the design of their first-generation and derivative products. After refinement steps within VCC, the HW/SW design and testbench infrastructure is exported using the VCC links to implementation features, and imported into the Mentor Graphics Seamless co-verification environment. With co-verification, the system-level decisions can be re-confirmed and the details of HW/SW interfaces analyzed. Together, co-design and co-verification provide a HW/SW development flow that assures design correctness before IC implementation.

"The link between VCC and Seamless is an important component of handset design flow," said Deepak Ahya, technologist and manager for Wireless Internet & Multimedia Platform Development for iDEN Subscriber Group, Motorola, a leading provider of wireless platforms. "Seamless satisfies our HW/SW verification needs while we use VCC to confirm our early architectural decisions and to efficiently interact within the design chain. I am very excited to see movement towards development of interfaces between architecture and design tools, leading someday to iDEN/Motorola's One Pass to Production vision."

About Cadence VCC

The VCC environment is a key component for system-on-chip (SoC) design methodologies. It enables designers to integrate virtual components representing both hardware and software, explore complex hardware and software tradeoffs, analyze product performance, and evaluate product architectures early in the development cycle. The VCC environment offers unique technologies for performance estimation, performance modeling, communication refinement, communication synthesis, and design export of hardware and software.

"This is an important milestone for VCC because the leading co-design environment now connects to the leading software-based co-verification environment," said Frank Schirrmeister, director product management, Advanced Verification and System Design at Cadence. "Using the customizable VCC links to implementation features, it was easy to connect both open infrastructures."

About Mentor Graphics Seamless

Combining the best in embedded software development tools with logic simulation, the Mentor Graphics Seamless co-verification environment delivers high performance co-verification months before a hardware prototype can be built. The Seamless environment enables software and hardware development to be parallel, removing the software from the critical path, and reducing the risk of hardware prototype iterations resulting from integration errors. User-controlled optimizations boost performance by isolating the logic simulator from software-intensive operations such as block memory transfers and algorithmic routines.

"To meet their design goals, customers must be able to rapidly create and verify designs as early as possible," said Serge Leef, general manager, System-on-Chip Verification Division, Mentor Graphics. "Customers requested this capability, and due to the open environment of Cadence VCC and Mentor Graphics Seamless, we are able to support this design environment."

Availability and Pricing

This joint flow is available today on Unix-based workstations from Sun Microsystems and Hewlett Packard.

Cadence VCC environment special packages for system integrators (VCC Evaluator) and for SoC providers (VCC Architect, including the Mentor Graphics Seamless link) are available now from Cadence. Pricing starts at $52,800 for a one-year license. For information regarding international pricing, please contact the local or regional Cadence sales office.

Mentor Graphics Seamless CVE is available now from $40,000 and can be obtained via Mentor Graphics' Co-Design web site or on CD for Sun and HP operating platforms. Seamless Processor Support Packages (PSP) start at $20,000 and are available through the same sources. To learn more about Seamless CVE or to register for a free Seamless workshop, visit the Mentor Graphics Web site at www.mentor.com/seamless.

About Cadence

Cadence is the largest supplier of electronic design automation products, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With 5,700 employees and 2000 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products, and services is available at www.cadence.com.

About Mentor Graphics

Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of more than $600 million and employs approximately 2,975 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.

Note to Editors: Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. Mentor Graphics and Seamless are registered trademarks and Co-Verification Environment and CVE are trademarks of Mentor Graphics Corporation. All other trademarks and registered trademarks are property of their respective holders.