Cadence Delivers Industry's First Tool Integrating Synthesis and Place-and-route Technologies.

SAN JOSE, Calif.--(BUSINESS WIRE)--July 12, 1999--

One-Pass, Signal Integrity-literate Implementation Flow Eases

Transition to 0.18 Micron

Cadence Design Systems (NYSE:CDN) today unveiled Envisia(TM) synthesis with physically knowledgeable synthesis (PKS) technology, the first electronic design automation (EDA) product to bring physically accurate timing to front-end synthesis. Cadence is working with system-on-a-chip (SOC) market leaders including Hewlett-Packard Co., NEC Electronics Inc., and IBM Co. to ensure the product meets the needs of leading-edge designers.

Envisia synthesis with PKS is the second deliverable this year in the Cadence(R) software and methodology roadmap for solving the challenges of designing electronics with process technologies of 0.18 micron and below. Envisia Silicon Ensemble(TM) ultra, introduced in January of this year, is the first product leveraging concurrent optimization technology for 0.18 micron and below.

"NEC has recently started working with the Cadence synthesis with PKS technology product," said Nobu Nishiguchi, senior engineering manager, ASIC EDA department at NEC. "Timing closure is an immense problem in the industry, and we are working with Cadence to obtain solutions for this problem."

The product is based upon a revolutionary concurrent optimization technology called PKS that simultaneously optimizes logical and physical design data against timing and physical constraints. The PKS technology integrates high-capacity register-transfer-level (RTL) synthesis, place-and-route, and timing optimization technologies. The result is a one-pass, signal integrity-literate implementation flow that improves overall productivity and restores predictability for deep-submicron (DSM) design.

"An integrated solution for synthesis, physical timing closure, and signal integrity requires superior technology in each of these areas. Considering these requirements, Cadence is the only company with the tool suites and methodology expertise capable of delivering a viable solution," said Shane Robison, president of the Design Productivity Group at Cadence, responsible for EDA products and services.

Delivers DSM Accuracy and High-Performance Designs

"We have worked with Cadence as a technology partner for some time on Envisia synthesis with PKS," said Richard Nash, High-Performance VLSI CAD manager for Hewlett-Packard's Integrated Circuit Business Division. "The key to reducing iterations is accurate route estimation in synthesis. In our experience, PKS-predicted routes had a significantly higher level of accuracy than with wire-load models, therefore reducing iterations."

Iterating from synthesis to place-and-route is one of the most acute problems in integrated circuit design. Envisia synthesis with PKS solves this problem by employing actual physical information, rather than statistical wire-load models, to calculate interconnect delays. Subsequently, it brings physical timing accuracy to RTL synthesis, where it has the greatest impact on productivity. Other approaches introduce physical timing late in the design cycle, after synthesis, as an additional cleanup step.

"Approaches that attempt to recover design performance after RTL synthesis are flawed because they require synthesis to produce a realizable design with inaccurate timing information," said Jeff Roane, director of synthesis product marketing for Cadence. "Envisia synthesis with PKS is the only product that solves the root problem -- RTL synthesis accuracy."

Envisia synthesis with PKS is built on top of the Envisia Ambit synthesis technology acquired by Cadence in 1998 and is ideal for multi-million-gate, high-performance designs. By eliminating the dependence on wire-load models for timing, the product eliminates unnecessary physical partitioning, resulting in higher performance designs.

"By achieving a more effective timing closure methodology, we will enable our customers to realize the full benefits of our leading technologies," said Karla Reynolds, ASIC CAD manager for timing and synthesis at IBM Microelectronics. "We are working with Cadence to meet our customers' demands for more accurate synthesis to achieve rapid timing closure for advanced fabrication processes."

One-Pass DSM Flow

Envisia synthesis with PKS achieves timing accuracy by integrating incremental placement and routing in the core synthesis loop. This integration allows PKS to employ the full set of logical synthesis transforms that are available in conventional synthesis tools. During PKS synthesis, each optimization is incrementally placed, routed, and timed, allowing millions of logical and physical tradeoffs against highly accurate timing. PKS achieves timing accuracy with a sophisticated delay calculator that computes interconnect delay from a layer-based, resistance capacitance (RC) model of the route. With placement based on Cadence's industry leading Envisia quadratic placer (formerly known as Qplace) technology, PKS achieves high-density results with timing correlation within 5 percent of final place and route. Following PKS synthesis, Silicon Ensemble ultra performs final physical design and signal integrity-based optimization. The end result of using PKS synthesis and the Silicon Ensemble ultra product is a one-pass, signal integrity-literate implementation flow with near-exact timing correlation throughout.

Envisia synthesis with PKS is designed to be plug-in compatible with the existing synthesis flow. The product takes in designs described in RTL or gate-level VHDL and Verilog(R), with timing and physical constraints. It synthesizes designs, producing a netlist with timing and physical constraints that are passed to place-and-route tools. In addition to a synthesis library, Envisia synthesis utilizes a physical library described in the popular Cadence Library Exchange Format (LEF).

In conjunction with the new PKS technology, Cadence also provides a set of methodology services to speed customer adoption. These services help customers rapidly integrate Cadence's one-pass DSM implementation and signal-integrity flow into their unique design environments.

Price and Availability

The Envisia synthesis with PKS tool is shipping today in limited production. It is U.S. list priced at $250,000.

About Cadence

Cadence Design Systems, Inc. is the largest supplier of software products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With more than 4,000 employees and 1998 annual sales of $1.2 billion, Cadence is headquartered in San Jose, Calif. and has sales offices, design centers, and research facilities located around the world. More information about the company, its products and services may be obtained from the World Wide Web at http://www.cadence.com.

Cadence, the Cadence logo, and Verilog are registered trademarks and Envisia and Silicon Ensemble are trademarks of Cadence Design Systems, Inc. All others are the properties of their holders.