Cadence Completes Acquisition of Plato Design Systems; Next-Generation Graph-Based Router to Enhance Cadence Technology Leadership at 0.13-Micron-and-Below Solutions.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--April 24, 2002

Cadence Design Systems, Inc. (NYSE:CDN), the world's leading supplier of electronic design products and services, today announced the completion of its acquisition of Plato Design Systems, Inc., a privately held design technology firm headquartered in San Jose. The financial terms of the agreement were not disclosed.

NanoRoute(TM), Plato's next-generation graph-based router, will improve the Cadence(R) SP&R (synthesis/place-and-route) technology with performance, timing and signal integrity enhancements targeted at 0.13-micron-and-below design. Initially, NanoRoute will be incorporated as an option into Cadence SoC Encounter(TM), Cadence's industry-leading hierarchical IC implementation technology.

"The acquisition of Plato is another major step in our strategy to integrate world-class technologies into Cadence's best-in-class solutions for chip designs at deep sub-micron process geometries," said Lavi Lev, executive vice president and general manager for Cadence IC business unit. "Additionally, Plato's world-class development team brings additional capability to Cadence's existing routing research and development group."

"This merger allows us to quickly deliver our technologies to many more customers and extends our ability to respond to customers' needs," said Limin He, president and CEO of Plato. "This also affords us a great opportunity to integrate our complementary technologies tightly with Cadence's technologies and help customers address the design challenges of deep sub-micron SoCs." All 26 Plato employees will join Cadence. Limin He will report to Ping Chao, Cadence senior vice president and general manager of Digital IC Solutions.

NanoRoute is a scalable routing and physical design optimization solution. By cutting routing time from days to hours, NanoRoute plays a key role in closing the gap between design productivity and advances in silicon technology. It will significantly enhance the current capabilities of Cadence SoC Encounter and First Encounter(R) Ultra by enabling designers to better meet deep sub-micron challenges in 0.13-micron-and below designs.

About Cadence

Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,600 employees and 2001 revenues of approximately $1.4 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services are available at www.cadence.com.

Except for historical information, the matters discussed in this release contain forward-looking statements based on current expectations or beliefs and are subject to factors and uncertainties that could cause actual results to differ materially from those described in the forward-looking statements. For a detailed discussion of these and other cautionary statements, please refer to Cadence's filings with the Securities and Exchange Commission. These include the Company's annual report on Form 10-K for the year ended December 29, 2001.

Note to Editors: Cadence and First Encounter are registered trademarks and NanoRoute is a trademark of Cadence Design Systems, Inc.